hdlsetup |
Set up model parameters for HDL code generation |
hdlsetuptoolpath |
Set up system environment to access FPGA synthesis software |
hdlset_param |
Set HDL-related parameters at model or block level |
hdlget_param |
Return value of specified HDL block-level parameter for specified block |
hdlsaveparams |
Save nondefault block- and model-level HDL parameters |
hdlrestoreparams |
Restore block- and model-level HDL parameters to model |
hdldispmdlparams |
Display HDL model parameters with nondefault values |
hdldispblkparams |
Display HDL block parameters with nondefault values |
| TargetLanguage | Specify HDL language to use for generated code |
| HDLMapFilePostfix | Specify postfix appended to file name for generated mapping file |
| TargetDirectory | Identify folder into which HDL Coder writes generated output files |
| VerilogFileExtension | Specify file type extension for generated Verilog files |
| VHDLFileExtension | Specify file type extension for generated VHDL files |
| UseSingleLibrary | Specify whether VHDL code generated for model references is in a single library, or in separate libraries |
| ClockEdge | Specify active clock edge |
| TriggerAsClock | Use trigger signal in triggered subsystem as a clock |
| OptimizeTimingController | Optimize timing controller entity by implementing separate counters per rate |
| TimingControllerArch | Generate reset for timing controller |
| Oversampling | Specify frequency of global oversampling clock as a multiple of model base rate |
| ResetAssertedLevel | Specify asserted (active) level of reset input signal |
| ResetLength | Define length of time (in clock cycles) during which reset is asserted |
| ResetType | Specify whether to use asynchronous or synchronous reset logic when generating HDL code for registers |
| NoResetInitializationMode | Specify whether you want to initialize registers without reset and the mode of initialization |
| AdaptivePipelining | Insert adaptive pipeline registers in your design |
| BalanceDelays | Set delay balancing for the model |
| LoopUnrolling | Specify whether VHDL FOR and GENERATE loops are unrolled and omitted from generated VHDL code |
| MaxComputationLatency | Specify the maximum number of time steps for which your DUT inputs are guaranteed to be stable |
| MaxOversampling | Limit the maximum sample rate |
| RAMMappingThreshold | Specify the minimum RAM size required for mapping to RAMs instead of registers |
| MapPipelineDelaysToRAM | Optimize for area by mapping pipeline registers in generated HDL code to RAM |
| TransformNonZeroInitDelay | Enable this property to optimize Delay blocks with non zero initial condition |
| DistributedPipeliningPriority | Specify priority for distributed pipelining algorithm |
| DistributedPipeliningBarriers | Highlight blocks that are inhibiting distributed pipelining |
| HierarchicalDistPipelining | Specify whether to apply retiming across a subsystem hierarchy |
| PreserveDesignDelays | Enable to prevent distributed pipelining from moving design delays |
| HighlightFeedbackLoops | Highlight feedback loops that can inhibit delay balancing and optimizations |
| ClockRatePipelining | Insert pipeline registers at the clock rate instead of the data rate for multi-cycle paths |
| ClockRatePipelineOutputPorts | Enable clock-rate pipelining for DUT ports |
| HighlightClockRatePipeliningDiagnostic | Highlight blocks that are inhibiting clock-rate pipelining |
| ShareAtomicSubsystems | Share atomic subsystems with resource sharing optimization |
| ShareFloatingPointIP | Share floating-point IP blocks with the resource sharing optimization |
| ShareMATLABBlocks | Share MATLAB Function blocks with resource sharing optimization |
| ShareMultipliers | Share multipliers with resource sharing optimization |
| MultiplierSharingMinimumBitwidth | Minimum bit width of shared multipliers for resource sharing optimization |
| MultiplierPartitioningThreshold | Multiplier partitioning input bit width threshold |
| MultiplierPromotionThreshold | Maximum word-length by which HDL Coder promotes a multiplier for sharing with other multipliers |
| ShareAdders | Share adders with resource sharing optimization |
| AdderSharingMinimumBitwidth | Minimum bitwidth of shared adders for resource sharing optimization |
| ClockEnableInputPort | Name HDL port for model's clock enable input signals |
| ClockEnableOutputPort | Specify name of clock enable output port |
| ClockInputPort | Name HDL port for model's clock input signals |
| ClockInputs | Specify generation of single or multiple clock inputs |
| EnablePrefix | Specify base name for internal clock enables in generated code |
| InputType | Specify HDL data type for model input ports |
| OutputType | Specify HDL data type for model output ports |
| ResetInputPort | Name HDL port for model's reset input |
| ScalarizePorts | Flatten vector ports into structure of scalar ports in VHDL code |
| BlockGenerateLabel | Specify postfix to block labels used for HDL GENERATE statements |
| CheckHDL | Check model or subsystem for HDL code generation compatibility |
| CriticalPathEstimation | Estimate critical path without running synthesis |
| DateComment | Specify whether to include time/date information in the generated HDL file header |
| GenerateHDLCode | Generate HDL code |
| GenerateValidationModel | Generate validation model with HDL code |
| HandleAtomicSubsystem | Enable reusable code generation for identical atomic subsystems |
| InitializeBlockRAM | Enable or suppress generation of initial signal value for RAM blocks |
| InlineConfigurations | Specify whether generated VHDL code includes inline configurations |
| InlineMATLABBlockCode | Inline HDL code for MATLAB Function blocks |
| InstanceGenerateLabel | Specify text to append to instance section labels in VHDL GENERATE statements |
| MaskParameterAsGeneric | Generate reusable HDL code for subsystems with identical mask parameters that differ only in value |
| MinimizeClockEnables | Omit generation of clock enable logic for single-rate designs |
| MinimizeIntermediateSignals | Specify whether to optimize HDL code for debuggability or code coverage |
| MulticyclePathInfo | Generate text file that reports multicycle path constraint information for use with synthesis tools |
| OutputGenerateLabel | Specify postfix to output assignment block labels for VHDL GENERATE statements |
| PipelinePostfix | Specify postfix to names of input or output pipeline registers generated for pipelined block implementations |
| RAMArchitecture | Select RAM architecture with or without clock enable for all RAMs in DUT subsystem |
| RequirementComments | Enable or disable generation of hyperlinked requirements comments in HTML code generation reports |
| SafeZeroConcat | Specify syntax for concatenated zeros in generated VHDL code |
| UserComment | Specify comment line in header of generated HDL and test bench files |
| Verbosity | Specify level of detail for messages displayed during code generation |
| UseAggregatesForConst | Specify whether constants are represented by aggregates, including constants that are less than 32 bits |
| UseRisingEdge | Specify VHDL coding style used to detect clock transitions |
| UseVerilogTimescale | Use compiler `timescale directives in generated Verilog code |
| HDLCodingStandard | Generate HDL code that follows the specified coding standard |
| HDLCodingStandardCustomizations | Specify HDL coding standard customization object |
| GenerateWebview | Include model Web view in the code generation report |
| OptimizationReport | Display HTML optimization report |
| ResourceReport | Display HTML resource utilization report |
| Traceability | Enable or disable creation of HTML code generation report with code-to-model and model-to-code hyperlinks |
| NativeFloatingPoint | Generate target-independent HDL code from single-precision floating-point models |
| ClockHighTime | Specify period, in nanoseconds, during which test bench drives clock input signals high (1) |
| ClockLowTime | Specify period, in nanoseconds, during which test bench drives clock input signals low (0) |
| DistributedPipeliningBarriersFile | Distributed pipelining barriers highlighting script name |
| ForceClock | Specify whether test bench forces clock input signals |
| ForceClockEnable | Specify whether test bench forces clock enable input signals |
| ForceReset | Specify whether test bench forces reset input signals |
| GenerateCoSimBlock | Generate HDL Cosimulation blocks for use in testing DUT |
| GenerateCoSimModel | Generate model containing HDL Cosimulation block for use in testing DUT |
| HighlightClockRatePipeliningFile | Clock-rate pipelining highlighting script name |
| HoldInputDataBetweenSamples | Specify how long subrate signal values are held in valid state |
| HoldTime | Specify hold time for input signals and forced reset input signals |
| IgnoreDataChecking | Specify number of samples during which output data checking is suppressed |
| InitializeTestBenchInputs | Specify initial value driven on test bench inputs before data is asserted to DUT |
| MultifileTestBench | Divide generated test bench into helper functions, data, and HDL test bench code files |
| SimulationLibPath | Specify the path to the compiled Altera or Xilinx simulation libraries |
| SimulatorFlags | Specify simulator flags to apply to generated compilation scripts |
| TestBenchClockEnableDelay | Define elapsed time in clock cycles between deassertion of reset and assertion of clock enable |
| TestBenchDataPostFix | Specify suffix added to test bench data file name when generating multifile test bench |
| TestBenchPostFix | Specify suffix to test bench name |
| TestBenchReferencePostFix | Specify text appended to names of reference signals generated in test bench code |
| UseFileIOInTestBench | Specify whether to use data files for reading and writing test bench stimulus and reference data |
| FPToleranceStrategy | Specify whether to check for floating-point tolerance based on relative error or ULP error |
| FPToleranceValue | Enter the tolerance value based on floating-point tolerance check setting |
| CodeGenerationOutput | Control production of generated code and display of generated model |
| GeneratedModelName | Specify name of generated model |
| GeneratedModelNamePrefix | Specify prefix to name of generated model |
| HighlightAncestors | Highlight ancestors of blocks in generated model that differ from original model |
| HighlightColor | Specify color for highlighted blocks in generated model |
| ClockProcessPostfix | Specify postfix to append to HDL clock process names |
| ComplexImagPostfix | Specify text to append to imaginary part of complex signal names |
| ComplexRealPostfix | Specify text to append to real part of complex signal names |
| DetectBlackBoxNameCollision | Check for duplicate module or entity names in generated code and black box interface code |
| EntityConflictPostfix | Specify postfix to duplicate VHDL entity or Verilog module names |
| InstancePostfix | Specify postfix to generated component instance names |
| InstancePrefix | Specify prefix to generated component instance names |
| PackagePostfix | Specify the postfix to append to specified model or subsystem name to form name of package file |
| ReservedWordPostfix | Specify postfix appended to identifiers for entities, signals, constants, or other model elements that conflict with VHDL or Verilog reserved words |
| SplitArchFilePostfix | Specify postfix to form name of file containing model VHDL architecture |
| SplitEntityArch | Specify whether generated VHDL entity and architecture code is written to single VHDL file or to separate files |
| SplitEntityFilePostfix | Specify postfix to form name of generated VHDL entity file |
| TimingControllerPostfix | Specify suffix appended to DUT name to form timing controller name |
| VectorPrefix | Specify prefix to vector names in generated code |
| VHDLArchitectureName | Specify architecture name for generated HDL code |
| VHDLLibraryName | Specify name of target library for generated HDL code |
| ModulePrefix | Specify prefix for DUT module or entity name |
| BlocksWithNoCharacterizationFile | Highlighting script for blocks without timing information in estimated critical path |
| CriticalPathEstimationFile | Critical path estimation highlighting script name |
| EDAScriptGeneration | Enable or disable generation of script files for third-party tools |
| HDLCompileInit | Specify text written to initialization section of compilation script |
| HDLCompileTerm | Specify text written to termination section of compilation script |
| HDLCompileFilePostfix | Specify postfix appended to file name for generated Mentor Graphics ModelSim compilation scripts |
| HDLCompileVerilogCmd | Specify command written to compilation script for Verilog files |
| HDLCompileVHDLCmd | Specify command written to compilation script for VHDL files |
| HDLLintCmd | Specify command written to HDL lint script |
| HDLLintInit | Specify HDL lint script initialization name |
| HDLLintTerm | Specify HDL lint script termination name |
| HDLLintTool | Select HDL lint tool for which HDL Coder generates scripts |
| HDLSimCmd | Specify command written to simulation script |
| HDLSimInit | Specify text written to initialization section of simulation script |
| HDLSimFilePostfix | Specify postfix appended to file name for generated Mentor Graphics ModelSim simulation scripts |
| HDLSimTerm | Specify text written to termination section of simulation script |
| HDLSimViewWaveCmd | Specify waveform viewing command written to simulation script |
| HDLSynthCmd | Specify command written to synthesis script |
| HDLSynthFilePostfix | Specify postfix appended to file name for generated synthesis scripts |
| HDLSynthInit | Specify text written to initialization section of synthesis script |
| HDLSynthTerm | Specify text written to termination section of synthesis script |
| HDLSynthTool | Select synthesis tool for which HDL Coder generates scripts |
| HighlightFeedbackLoopsFile | Feedback loop highlighting script file name |
HDL Code Generation from a Simulink Model
Hands-on introduction to the mechanics of generating VHDL® and Verilog® code and test benches from models
Set HDL Code Generation Options
How to access HDL options in the Configuration Parameters dialog box and Model Explorer; the HDL Code context menu; pointers to related information
How to view HDL parameter settings at the block and model level
Add or Remove the HDL Configuration Component
Adding an HDL configuration component to make models more portable
Set and View HDL Block Parameters
How to view or set the implementation parameters for a block
Set HDL Block Parameters for Multiple Blocks
How to configure implementations for a group of blocks
HDL code generation parameters supported for specific block implementations