Settings

'base name'

Default: 'enb'

Specify the base name as a character vector. HDL Coder™ uses the base name for internal clock enables and other flow control signals in generated code.

Usage Notes

Where only a single clock enable is generated, EnablePrefix specifies the signal name for the internal clock enable signal.

In some cases multiple clock enables are generated (for example, when a cascade block implementation for certain blocks is specified). In such cases, EnablePrefix specifies a base signal name for the first clock enable that is generated. For other clock enable signals, numeric tags are appended to EnablePrefix to form unique signal names. For example, the following code fragment illustrates two clock enables that were generated when EnablePrefix was set to 'test_clk_enable' :

COMPONENT mysys_tc
    PORT( clk                   :   IN    std_logic;
          reset                 :   IN    std_logic;
          clk_enable            :   IN    std_logic;
          test_clk_enable       :   OUT   std_logic;
          test_clk_enable_5_1_0 :   OUT   std_logic
          );
  END COMPONENT;

Set or View This Property

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.