Settings

'Single' (Default)

Generates a single clock input for the DUT. If the DUT is multirate, the input clock is the master clock rate, and a timing controller is synthesized to generate additional clocks as required.

'Multiple'

Generates a unique clock for each Simulink^® rate in the DUT. The number of timing controllers generated depends on the contents of the DUT.

Usage Notes

The oversample factor must be 1 (default) to specify multiple clocks.

Set or View This Property

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

Example

The following example specifies the generation of multiple clocks.

makehdl(gcb, 'ClockInputs','Multiple');