Generate HDL RTL code from model, subsystem, or model reference
makehdl( generates
HDL code from the specified DUT model, subsystem, or model reference
with options specified by one or more name-value pair arguments.dut,Name,Value)
Generate VHDL® code for the current model.
Generate HDL code for the current model with code generation options set to default values.
makehdl(bdroot)
The generated VHDL code is saved in the hdlsrc folder.
Generate Verilog® for the subsystem symmetric_fir within
the model sfir_fixed.
Open the sfir_fixed model.
sfir_fixed;
The model opens in a new Simulink® window.
Generate Verilog for the symmetric_fir subsystem.
makehdl('sfir_fixed/symmetric_fir','TargetLanguage','Verilog')
### Generating HDL for 'sfir_fixed/symmetric_fir'.
### Starting HDL check.
### HDL check for 'sfir_fixed' complete with 0 errors, 0 warnings,
and 0 messages.
### Begin Verilog Code Generation for 'sfir_fixed'.
### Working on sfir_fixed/symmetric_fir as
hdlsrc\sfir_fixed\symmetric_fir.v
### HDL code generation complete.The generated Verilog code for the symmetric_fir subsystem
is saved in hdlsrc\sfir_fixed\symmetric_fir.v.
Close the model.
bdclose('sfir_fixed');Check that the subsystem symmetric_fir is
compatible with HDL code generation, then generate HDL.
Open the sfir_fixed model.
sfir_fixed;
The model opens in a new Simulink window.
Check the symmetric_fir subsystem for
compatibility with HDL code generation. Generate code with code generation
options set to default values.
makehdl('sfir_fixed/symmetric_fir','CheckHDL','on')
The generated VHDL code for the symmetric_fir subsystem
is saved in hdlsrc\sfir_fixed\symmetric_fir.vhd.
Close the model.
bdclose('sfir_fixed');dut — DUT model or subsystem nameSpecified as subsystem name, top-level model name, or model reference name with full hierarchical path.
Example: 'top_level_name'
Example: 'top_level_name/subsysA/subsysB/codegen_subsys_name'
Specify optional comma-separated pairs of Name,Value arguments.
Name is the argument
name and Value is the corresponding
value. Name must appear
inside single quotes (' ').
You can specify several name and value pair
arguments in any order as Name1,Value1,...,NameN,ValueN.
‘TargetLanguage','Verilog''TargetLanguage' — Target language'VHDL' (default) | 'Verilog'For more information, see TargetLanguage.
'TargetDirectory' — Output directory'hdlsrc' (default) | character vectorFor more information, see TargetDirectory.
'CheckHDL' — Check HDL code generation compatibility'off' (default) | 'on'For more information, see CheckHDL.
'GenerateHDLCode' — Generate HDL code'on' (default) | 'off'For more information, see GenerateHDLCode.
'SplitEntityArch' — Split VHDL entity and architecture into separate files'off' (default) | 'on'For more information, see SplitEntityArch.
'UseSingleLibrary' — Generate VHDL code for model references into a single library'off' (default) | 'on'For more information, see UseSingleLibrary.
'Verbosity' — Level of message detail1 (default) | 0For more information, see Verbosity.
'HDLCodingStandard' — Specify HDL coding standardFor more information, see HDLCodingStandard.
'HDLCodingStandardCustomizations' — Specify HDL coding standard customization objecthdlcoder.CodingStandard objectFor more information, see HDLCodingStandardCustomizations.
'Traceability' — Generate report with mapping links between HDL and model'off' (default) | 'on'For more information, see Traceability.
'ResourceReport' — Resource utilization report generation'off' (default) | 'on'For more information, see ResourceReport.
'OptimizationReport' — Optimization report generation'off' (default) | 'on'For more information, see OptimizationReport.
'GenerateWebview' — Include model Web view'on' (default) | 'off'For more information, see GenerateWebview.
'BalanceDelays' — Delay balancing'on' (default) | 'off'For more information, see BalanceDelays.
'DistributedPipeliningPriority' — Specify priority for distributed pipelining algorithm'NumericalIntegrity' (default) | 'Performance'For more information, see DistributedPipeliningPriority.
'HierarchicalDistPipelining' — Hierarchical distributed pipelining'off' (default) | 'on'For more information, see HierarchicalDistPipelining.
'PreserveDesignDelays' — Prevent distributed pipelining from moving design delays'off' (default) | 'on'For more information, see PreserveDesignDelays.
'ClockRatePipelining' — Insert pipeline registers at the clock rate instead of the data rate for multi-cycle paths'on' (default) | 'off'For more information, see ClockRatePipelining.
'MaxOversampling' — Limit the maximum sample rateFor more information, see MaxOversampling.
'MaxComputationLatency' — Specify the maximum number of time steps for which your DUT inputs are guaranteed to be stableFor more information, see MaxComputationLatency.
'MinimizeClockEnables' — Omit clock enable logic for single-rate designs'off' (default) | 'on'For more information, see MinimizeClockEnables.
'RAMMappingThreshold' — Minimum RAM size for mapping to RAMs instead of registersThe minimum RAM size required for mapping to RAMs instead of registers, specified in bits.
For more information, see RAMMappingThreshold.
'MapPipelineDelaysToRAM' — Map pipeline registers in the generated HDL code to RAM'off' (default) | 'on'For more information, see MapPipelineDelaysToRAM.
'HighlightFeedbackLoops' — Highlight feedback loops inhibiting delay balancing and optimizations'off' (default) | 'on'For more information, see HighlightFeedbackLoops.
'HighlightFeedbackLoopsFile' — Feedback loop highlighting script file name'highlightFeedbackLoop' (default) | character vectorFor more information, see HighlightFeedbackLoopsFile.
'UserComment' — HDL file header commentFor more information, see UserComment.
'UseAggregatesForConst' — Represent constant values with aggregates'off' (default) | 'on'For more information, see UseAggregatesForConst.
'UseRisingEdge' — Use VHDL rising_edge or falling_edge function to detect clock transitions'off' (default) | 'on'For more information, see UseRisingEdge.
'LoopUnrolling' — Unroll VHDL FOR and GENERATE loops'off' (default) | 'on'For more information, see LoopUnrolling.
'UseVerilogTimescale' — Generate 'timescale compiler directives'on' (default) | 'off'For more information, see UseVerilogTimescale.
'InlineConfigurations' — Include VHDL configurations'on' (default) | 'off'For more information, see InlineConfigurations.
'SafeZeroConcat' — Type-safe syntax for concatenated zeros'on' (default) | 'off'For more information, see SafeZeroConcat.
'DateComment' — Include time stamp in header'on' (default) | 'off'For more information, see DateComment.
'ScalarizePorts' — Flatten vector ports into scalar ports'off' (default) | 'on'For more information, see ScalarizePorts.
'MinimizeIntermediateSignals' — Minimize intermediate signals'off' (default) | 'on'For more information, see MinimizeIntermediateSignals.
'RequirementComments' — Link from code generation reports to requirement documents'on' (default) | 'off'For more information, see RequirementComments.
'InlineMATLABBlockCode' — Inline HDL code for MATLAB Function blocks'off' (default) | 'on'For more information, see InlineMATLABBlockCode.
'MaskParameterAsGeneric' — Reusable code generation for subsystems with identical mask parameters'off' (default) | 'on'For more information, see MaskParameterAsGeneric.
'InitializeBlockRAM' — Initial signal value generation for RAM blocks'on' (default) | 'off'For more information, see InitializeBlockRAM.
'RAMArchitecture' — RAM architecture'WithClockEnable' (default) | 'WithoutClockEnable'For more information, see RAMArchitecture.
'HandleAtomicSubsystem' — Reusable code generation for identical atomic subsystems'on' (default) | 'off'For more information, see HandleAtomicSubsystem.
'ClockEdge' — Active clock edge'Rising' (default) | 'Falling'For more information, see ClockEdge.
'ClockInputs' — Single or multiple clock inputs'Single' (default) | 'Multiple'For more information, see ClockInputs.
'Oversampling' — Oversampling factor for global clock1 (default) | integer greater than or equal to 0Frequency of global oversampling clock, specified as an integer multiple of the model's base rate.
For more information, see Oversampling.
'ResetAssertedLevel' — Asserted (active) level of reset'active-high' (default) | 'active-low'For more information, see ResetAssertedLevel.
'ResetType' — Reset type'async' (default) | 'sync'For more information, see ResetType.
'TriggerAsClock' — Use trigger signal as clock in triggered subsystems'off' (default) | 'on'For more information, see TriggerAsClock.
'TimingControllerArch' — Generate reset for timing controller'default' (default) | 'resettable'For more information, see TimingControllerArch.
'Verbosity' — Level of message detailnFor more information, see Verbosity.
'GenerateCoSimBlock' — Generate HDL Cosimulation block'off' (default) | 'on'Generate an HDL Cosimulation block so you can simulate the DUT in Simulink with an HDL simulator.
For more information, see GenerateCoSimBlock.
'GenerateCoSimModel' — Generate HDL Cosimulation model'ModelSim' (default) | 'Incisive' | 'None'Generate a model containing an HDL Cosimulation block for the specified HDL simulator.
For more information, see GenerateCoSimModel.
'GenerateValidationModel' — Generate validation model'off' (default) | 'on'For more information, see GenerateValidationModel.
'SimulatorFlags' — Options for generated compilation scriptsFor more information, see SimulatorFlags.
'TestBenchReferencePostFix' — Suffix for test bench reference signals'_ref' (default) | character vectorFor more information, see TestBenchReferencePostFix.
'EDAScriptGeneration' — Enable or disable script generation for third-party tools'on' (default) | 'off'For more information, see EDAScriptGeneration.
'HDLCompileInit' — Compilation script initialization text'vlib work\n' (default) | character vectorFor more information, see HDLCompileInit.
'HDLCompileTerm' — Compilation script termination text'' (default) | character vectorFor more information, see HDLCompileTerm.
'HDLCompileFilePostfix' — Postfix for compilation script file name'_compile.do' (default) | character vectorFor more information, see HDLCompileFilePostfix.
'HDLCompileVerilogCmd' — Verilog compilation command'vlog %s %s\n' (default) | character vectorVerilog compilation command, specified as a character vector.
The SimulatorFlags name-value pair specifies the
first argument, and the module name specifies the second argument.
For more information, see HDLCompileVerilogCmd.
'HDLCompileVHDLCmd' — VHDL compilation command'vcom %s %s\n' (default) | character vectorVHDL compilation command, specified as a character vector.
The SimulatorFlags name-value pair specifies the
first argument, and the entity name specifies the second argument.
For more information, see HDLCompileVHDLCmd.
'HDLLintTool' — HDL lint tool'None' (default) | 'AscentLint' | 'Leda' | 'SpyGlass' | 'Custom'For more information, see HDLLintTool.
'HDLLintInit' — HDL lint initialization nameHDL lint initialization name, specified as a character vector.
The default is derived from the HDLLintTool name-value
pair.
For more information, see HDLLintInit.
'HDLLintCmd' — HDL lint commandHDL lint command, specified as a character vector. The default
is derived from the HDLLintTool name-value pair.
For more information, see HDLLintCmd.
'HDLLintTerm' — HDL lint termination nameHDL lint termination, specified as a character vector. The default
is derived from the HDLLintTool name-value pair.
For more information, see HDLLintTerm.
'HDLSynthTool' — Synthesis tool'None' (default) | 'ISE' | 'Libero' | 'Precision' | 'Quartus' | 'Synplify' | 'Vivado' | 'Custom'For more information, see HDLSynthTool.
'HDLSynthCmd' — HDL synthesis commandHDL synthesis command, specified as a character vector. The
default is derived from the HDLSynthTool name-value
pair.
For more information, see HDLSynthCmd.
'HDLSynthFilePostfix' — Postfix for synthesis script file nameHDL synthesis script file name postfix, specified as a character
vector. The default is derived from the HDLSynthTool name-value
pair.
For more information, see HDLSynthFilePostfix.
'HDLSynthInit' — Synthesis script initialization nameInitialization for the HDL synthesis script, specified as a
character vector. The default is derived from the HDLSynthTool name-value
pair.
For more information, see HDLSynthInit.
'HDLSynthTerm' — Synthesis script termination nameTermination name for the HDL synthesis script. The default is
derived from the HDLSynthTool name-value pair.
For more information, see HDLSynthTerm.
'CodeGenerationOutput' — Display and generation of generated model'GenerateHDLCode' (default) | 'GenerateHDLCodeAndDisplayGeneratedModel' | 'DisplayGeneratedModelOnly'For more information, see CodeGenerationOutput.
'GeneratedModelName' — Generated model nameFor more information, see GeneratedModelName.
'GeneratedModelNamePrefix' — Prefix for generated model name'gm_' (default) | character vectorFor more information, see GeneratedModelNamePrefix.
'HighlightAncestors' — Highlight parent blocks of generated model blocks differing from original model'on' (default) | 'off'For more information, see HighlightAncestors.
'HighlightColor' — Color of highlighted blocks in generated model'cyan' (default) | 'yellow' | 'magenta' | 'red' | 'green' | 'blue' | 'white' | 'magenta' | 'black'For more information, see HighlightColor.
'SynthesisTool' — Synthesis tool'' (default) | 'Altera Quartus II' | 'Xilinx ISE' | 'Xilinx Vivado'For more information, see SynthesisTool.
'MulticyclePathInfo' — Multicycle path constraint file generation'off' (default) | 'on'For more information, see MulticyclePathInfo.
'ClockEnableInputPort' — Clock enable input port name'clk_enable' (default) | character vectorClock enable input port name, specified as a character vector.
For more information, see ClockEnableInputPort.
'ClockEnableOutputPort' — Clock enable output port name'ce_out' (default) | character vectorClock enable output port name, specified as a character vector.
For more information, see ClockEnableOutputPort.
'ClockInputPort' — Clock input port name'clk' (default) | character vectorClock input port name, specified as a character vector.
For more information, see ClockInputPort.
'InputType' — HDL data type for input ports'wire' or 'std_logic_vector' (default) | 'signed/unsigned'VHDL inputs can have 'std_logic_vector' or 'signed/unsigned' data
type. Verilog inputs must be 'wire'.
For more information, see InputType.
'OutputType' — HDL data type for output ports'Same as input data type' (default) | 'std_logic_vector' | 'signed/unsigned' | 'wire'VHDL output can be 'Same as input data type', 'std_logic_vector' or 'signed/unsigned'. Verilog output
must be 'wire'.
For more information, see OutputType.
'ResetInputPort' — Reset input port name'reset' (default) | character vectorReset input port name, specified as a character vector.
For more information, see ResetInputPort.
'VerilogFileExtension' — Verilog file extension'.v' (default) | character vectorFor more information, see VerilogFileExtension.
'VHDLFileExtension' — VHDL file extension'.vhd' (default) | character vectorFor more information, see VHDLFileExtension.
'VHDLArchitectureName' — VHDL architecture name'rtl' (default) | character vectorFor more information, see VHDLArchitectureName.
'VHDLLibraryName' — VHDL library name'work' (default) | character vectorFor more information, see VHDLLibraryName.
'SplitEntityFilePostfix' — Postfix for VHDL entity file names'_entity' (default) | character vectorFor more information, see SplitEntityFilePostfix.
'SplitArchFilePostfix' — Postfix for VHDL architecture file names'_arch' (default) | character vectorFor more information, see SplitArchFilePostfix.
'PackagePostfix' — Postfix for package file name'_pkg' (default) | character vectorFor more information, see PackagePostfix.
'HDLMapFilePostfix' — Postfix for mapping file'_map.txt' (default) | character vectorFor more information, see HDLMapFilePostfix.
'BlockGenerateLabel' — Block label postfix for VHDL GENERATE statements'_gen' (default) | character vectorFor more information, see BlockGenerateLabel.
'ClockProcessPostfix' — Postfix for clock process names'_process' (default) | character vectorFor more information, see ClockProcessPostfix.
'ComplexImagPostfix' — Postfix for imaginary part of complex signal'_im' (default) | character vectorFor more information, see ComplexImagPostfix.
'ComplexRealPostfix' — Postfix for imaginary part of complex signal names'_re' (default) | character vectorFor more information, see ComplexRealPostfix.
'EntityConflictPostfix' — Postfix for duplicate VHDL entity or Verilog module names'_block' (default) | character vectorFor more information, see EntityConflictPostfix.
'InstanceGenerateLabel' — Instance section label postfix for VHDL GENERATE statements'_gen' (default) | character vectorFor more information, see InstanceGenerateLabel.
'InstancePostfix' — Postfix for generated component instance names'' (default) | character vectorFor more information, see InstancePostfix.
'InstancePrefix' — Prefix for generated component instance names'u_' (default) | character vectorFor more information, see InstancePrefix.
'OutputGenerateLabel' — Output assignment label postfix for VHDL GENERATE statements'outputgen' (default) | character vectorFor more information, see OutputGenerateLabel.
'PipelinePostfix' — Postfix for input and output pipeline register names'_pipe' (default) | character vectorFor more information, see PipelinePostfix.
'ReservedWordPostfix' — Postfix for names conflicting with VHDL or Verilog reserved words'_rsvd' (default) | character vectorFor more information, see ReservedWordPostfix.
'TimingControllerPostfix' — Postfix for timing controller name'_tc' (default) | character vectorFor more information, see TimingControllerPostfix.
'VectorPrefix' — Prefix for vector names'vector_of_' (default) | character vectorFor more information, see VectorPrefix.
'EnablePrefix' — Prefix for internal enable signals'enb' (default) | character vectorPrefix for internal clock enable and control flow enable signals, specified as a character vector.
For more information, see EnablePrefix.
'ModulePrefix' — Prefix for modules or entity names'' (default) | character vectorSpecify a prefix for every module or entity name in the generated HDL code. HDL Coder™ also applies this prefix to generated script file names
For more information, see ModulePrefix.