Generate a Board-Independent IP Core from Simulink
To generate a board-independent custom IP core to use in an embedded system integration environment, such as Altera® Qsys, Xilinx® EDK, or Xilinx IP Integrator:To learn more about custom IP core generation, see Custom IP Core Generation.
Using the HDL Workflow Advisor, you can generate a custom IP core from a model or algorithm.
You generate an HTML custom IP core report by default when you generate a custom IP core.
Processor and FPGA Synchronization
In the HDL Workflow Advisor, you can choose a Processor/FPGA synchronization mode for your processor and FPGA when you:The following synchronization modes are available: