Insert pipeline registers at the clock rate instead of the data rate for multi-cycle paths
'on' (default)
Insert pipeline registers at clock rate for multi-cycle paths.
'off'
Insert pipeline registers at data rate for multi-cycle paths.
You can further control clock-rate pipelining within the model by disabling or enabling delay balancing for subsystems within the model.
To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.