Documentation

Overview

Block implementation parameters enable you to control details of the code generated for specific block implementations. See Set and View HDL Block Parameters to learn how to select block implementations and parameters in the GUI or the command line.

Property names are specified as character vectors. The data type of a property value is specific to the property. This section describes the syntax of each block implementation parameter and how the parameter affects generated code.

AdaptivePipelining

The AdaptivePipelining subsystem parameter enables you to set adaptive pipelining on a subsystem within a model.

To disable adaptive pipelining for a subsystem within a model, set the adaptive pipelining parameter, AdaptivePipelining, to 'off' for that subsystem.

To learn how to set model-level adaptive pipelining, see AdaptivePipelining.

Set Adaptive Pipelining For a Subsystem

To set adaptive pipelining for a subsystem from the HDL Block Properties dialog box:

1. Right-click the subsystem.

2. Select HDL Code > HDL Block Properties .

3. For AdaptivePipelining, select inherit, on, or off.

To set adaptive pipelining for a subsystem from the command line, use hdlset_param. For example, to turn off adaptive pipelining for a subsystem, my_dut:

hdlset_param('my_dut', 'AdaptivePipelining', 'off')

BalanceDelays

The BalanceDelays subsystem parameter enables you to set delay balancing on a subsystem within a model.

To disable delay balancing for any subsystem within a model, you must set the model-level delay balancing parameter, BalanceDelays, to 'off'.

To learn how to set model-level delay balancing, see BalanceDelays.

Set Delay Balancing For a Subsystem

To set delay balancing for a subsystem using the HDL Block Properties dialog box:

1. Right-click the subsystem.

2. Select HDL Code > HDL Block Properties .

3. For BalanceDelays, select inherit, on, or off.

To set delay balancing for a subsystem from the command line, use hdlset_param. For example, to turn off delay balancing for a subsystem, my_dut:

hdlset_param('my_dut', 'BalanceDelays', 'off')

ClockRatePipelining

The ClockRatePipelining subsystem parameter enables you to set clock-rate pipelining on a subsystem within a model.

To disable clock-rate pipelining for a subsystem within a model, set the clock-rate pipelining parameter, ClockRatePipelining, to 'off' for that subsystem.

To learn how to set model-level clock-rate pipelining, see ClockRatePipelining.

Set Clock-Rate Pipelining For a Subsystem

To set clock-rate pipelining for a subsystem using the HDL Block Properties dialog box:

1. Right-click the subsystem.

2. Select HDL Code > HDL Block Properties .

3. For ClockRatePipelining, select inherit, on, or off.

To set clock-rate pipelining for a subsystem from the command line, use hdlset_param. For example, to turn off clock-rate pipelining for a subsystem, my_dut:

hdlset_param('my_dut', 'ClockRatePipelining', 'off')

ConstMultiplierOptimization

The ConstMultiplierOptimization implementation parameter lets you specify use of canonical signed digit (CSD) or factored CSD optimizations for processing coefficient multiplier operations in the generated code.

The following table shows the ConstMultiplierOptimization parameter values.

The ConstMultiplierOptimization parameter is available for the following blocks:

• Gain

• Stateflow^® chart

• Truth Table

• MATLAB Function

• MATLAB System

ConstrainedOutputPipeline

Use the ConstrainedOutputPipeline parameter to specify a nonnegative number of registers to place at the block outputs.

HDL Coder moves existing delays within your design to try to meet your constraint. New registers are not added. If there are fewer registers than the coder needs to satisfy your constraint, the coder reports the difference between the number of desired and actual output registers. You can add delays to your design using input or output pipelining.

Distributed pipelining does not redistribute registers you specify with constrained output pipelining.

How to Specify Constrained Output Pipelining

To specify constrained output pipelining for a block using the GUI:

1. Right-click the block and select HDL Code > HDL Block Properties.

2. For ConstrainedOutputPipeline, enter the number of registers you want at the output ports.

To specify constrained output pipelining, at the command line, enter:

hdlset_param(path_to_block,
             'ConstrainedOutputPipeline', number_of_output_registers)

hdlset_param('mymodel/subsys','ConstrainedOutputPipeline', 6)

See Also

• Constrained Output Pipelining

DistributedPipelining

The DistributedPipelining parameter enables pipeline register distribution, a speed optimization that enables you to increase your clock speed by reducing your critical path.

The following table shows the effect of the DistributedPipelining and OutputPipeline parameters.

To achieve further optimization of code generated with distributed pipelining, perform retiming during RTL synthesis, if possible.

Tip   Output data might be in an invalid state initially if you insert pipeline registers. To avoid test bench errors resulting from initial invalid samples, disable output checking for those samples. For more information, see: Ignore output data checking (number of samples) IgnoreDataChecking

See Also

• Distributed Pipelining and Hierarchical Distributed Pipelining

• Specify Distributed Pipelining

• Distributed Pipeline Insertion for MATLAB Function Blocks

DSPStyle

DSPStyle enables you to generate code that includes synthesis attributes for multiplier mapping in your design. You can choose whether to map a particular block's multipliers to DSPs or logic in hardware.

For Xilinx^® targets, the generated code uses the use_dsp48 attribute. For Altera^® targets, the generated code uses the multstyle attribute.

The DSPStyle options are listed in the following table.

The DSPStyle parameter is available for the following blocks:

• Gain

• Product

• Product of Elements with Architecture set to Tree

• Subsystem

• Atomic Subsystem

• Variant Subsystem

• Enabled Subsystem

• Triggered Subsystem

• Model, Model Variants with Architecture set to ModelReference

Hierarchy Flattening Behavior

If you specify hierarchy flattening for a subsystem that also has a nondefault DSPStyle setting, HDL Coder propagates the DSPStyle setting to the parent subsystem.

If the flattened subsystem contains Gain, Product, or Product of Elements blocks, the coder keeps their nondefault DSPStyle settings, and replaces default DSPStyle settings with the flattened subsystem DSPStyle setting.

Synthesis Attributes in Generated Code

The generated code for synthesis attributes depends on:

• Target language

• DSPStyle value

• SynthesisTool value

The following table shows examples of synthesis attributes in generated code.

Requirement For Synthesis Attribute Specification

You must specify a synthesis tool by using the SynthesisTool property.

How To Specify a Synthesis Attribute

To specify a synthesis attribute using the HDL Block Properties dialog box:

1. Right-click the block.

2. Select HDL Code > HDL Block Properties .

3. For DSPStyle, select on, off, or none.

To specify a synthesis attribute from the command line, use hdlset_param. For example, suppose you have a model, my_model, with a DUT subsystem, my_dut, that contains a . Gain block, my_multiplier. To insert a synthesis attribute to map my_multiplier to a DSP, enter:

hdlset_param('my_model/my_dut/my_multiplier', 'DSPStyle', 'on')

Limitations For Synthesis Attribute Specification

• When you specify a nondefault DSPStyle block property, the ConstMultiplierOptimization property must be set to 'none'.

• Inputs to multiplier components cannot use the double data type.

• Gain constant cannot be a power of 2.

FlattenHierarchy

FlattenHierarchy enables you to remove subsystem hierarchy from the HDL code generated from your design.

Prerequisites For Hierarchy Flattening

To flatten hierarchy, a subsystem must have the following block properties.

To flatten hierarchy, you must also have the MaskParameterAsGeneric global property set to 'off'. For more information, see MaskParameterAsGeneric.

How To Flatten Hierarchy

To set hierarchy flattening using the HDL Block Properties dialog box:

1. Right-click the subsystem.

2. Select HDL Code > HDL Block Properties .

3. For FlattenHierarchy, select on, off, or inherit.

To set hierarchy flattening from the command line, use hdlset_param. For example, to turn on hierarchy flattening for a subsystem, my_dut:

hdlset_param('my_dut', 'FlattenHierarchy', 'on')

Limitations For Hierarchy Flattening

A subsystem cannot be flattened if the subsystem is:

• A black box implementation or model reference.

• A triggered subsystem when TriggerAsClock is enabled.

• A masked subsystem that contains any of the following:

  • Bus.

  • Enumerated data type.

  • Lookup table block: 1-D Lookup Table, 2-D Lookup Table, Cosine, Direct LookupTable (n-D), Prelookup, Sine, n-D Lookup Table.

  • MATLAB Function block.

  • MATLAB System block.

  • Stateflow block: Chart, State Transition Table, Message Viewer.

  • Block with a pass-through or no-op implementation. See Pass through, No HDL, and Cascade Implementations.

Note:   This option removes subsystem boundaries before code generation. It does not necessarily generate HDL code with a completely flat hierarchy.

InputPipeline

InputPipeline lets you specify a implementation with input pipelining for selected blocks. The parameter value specifies the number of input pipeline stages (pipeline depth) in the generated code.

The following code specifies an input pipeline depth of two stages for each Sum block in the model:

sblocks = find_system(gcb, 'BlockType', 'Sum');
for ii=1:length(sblocks),hdlset_param(sblocks{ii},'InputPipeline', 2), end;

When generating code for pipeline registers, HDL Coder appends a postfix string to names of input or output pipeline registers. The default postfix string is _pipe. To customize the postfix string, use the Pipeline postfix option in the Global Settings / General pane in the HDL Code Generation pane of the Configuration Parameters dialog box. Alternatively, you can pass the desired postfix as a character vector in the makehdl property PipelinePostfix. See PipelinePostfix for an example.

InstantiateFunctions

For the MATLAB Function block, you can use the InstantiateFunctions parameter to generate a VHDL^® entity or Verilog^® module for each function. HDL Coder generates code for each entity or module in a separate file.

The InstantiateFunctions options for the MATLAB Function block are listed in the following table.

How To Generate Instantiable Code for Functions

To set the InstantiateFunctions parameter using the HDL Block Properties dialog box:

1. Right-click the MATLAB Function block.

2. Select HDL Code > HDL Block Properties.

3. For InstantiateFunctions, select on.

To set the InstantiateFunctions parameter from the command line, use hdlset_param. For example, to generate instantiable code for functions in a MATLAB Function block, myMatlabFcn, in your DUT subsystem, myDUT, enter:

hdlset_param('my_DUT/my_MATLABFcnBlk', 'InstantiateFunctions', 'on')

Generate Code Inline for Specific Functions

If you want to generate instantiable code for some functions but not others, enable the option to generate instantiable code for functions, and use coder.inline. See coder.inline for details.

Limitations for Instantiable Code Generation for Functions

The software generates code inline when:

• Function calls are within conditional code or for loops.

• Any function is called with a nonconstant struct input.

• The function has state, such as a persistent variable, and is called multiple times.

• There is an enumeration anywhere in the design function.

If you enable InstantiateFunctions, UseMatrixTypesInHDL has no effect.

InstantiateStages

For a Cascade architecture, you can use the InstantiateStages parameter to generate a VHDL entity or Verilog module for each computation stage. HDL Coder generates code for each entity or module in a separate file.

LoopOptimization

LoopOptimization enables you to stream or unroll loops in code generated from a MATLAB Function block. Loop streaming optimizes for area; loop unrolling optimizes for speed.

How to Optimize MATLAB Function Block For Loops

To select a loop optimization using the HDL Block Properties dialog box:

1. Right-click the MATLAB Function block.

2. Select HDL Code > HDL Block Properties.

3. For LoopOptimization, select none, Unrolling, or Streaming.

To select a loop optimization from the command line, use hdlset_param. For example, to turn on loop streaming for a MATLAB Function block, my_mlfn:

hdlset_param('my_mlfn', 'LoopOptimization', 'Streaming')

Limitations for MATLAB Function Block Loop Optimization

HDL Coder cannot stream a loop if:

• The loop index counts down. The loop index must increase by 1 on each iteration.

• There are 2 or more nested loops at the same level of hierarchy within another loop.

• Any particular persistent variable is updated both inside and outside a loop.

HDL Coder can stream a loop when the persistent variable is:

• Updated inside the loop and read outside the loop.

• Read within the loop and updated outside the loop.

LUTRegisterResetType

Use the LUTRegisterResetType block parameter to control synthesis of a LUT into a ROM structure on an FPGA.

You can specify LUTRegisterResetType for the following blocks:

• NCO HDL Optimized

• Gamma Correction

• Lookup Table

MapPersistentVarsToRAM

With the MapPersistentVarsToRAM implementation parameter, you can use RAM-based mapping for persistent arrays of a MATLAB Function block instead of mapping to registers.

RAM Mapping Restrictions

When you enable RAM mapping, a persistent array or user-defined System object™ private property maps to a block RAM when all of the following conditions are true:

• Each read or write access is for a single element only. For example, submatrix access and array copies are not allowed.

• Address computation logic is not read-dependent. For example, computation of a read or write address using the data read from the array is not allowed.

• Persistent variables or user-defined System object private properties are initialized to 0 if they have a cyclic dependency. For example, if you have two persistent variables, A and B, you have a cyclic dependency if A depends on B, and B depends on A.

• If an access is within a conditional statement, the conditional statement uses only simple logic expressions (&&, ||, ~) or relational operators. For example, in the following code, r1 does not map to RAM:

  if (mod(i,2) > 0)
      a = r1(u);
  else
      r1(i) = u;
  end 

  Rewrite complex conditions, such as conditions that call functions, by assigning them to temporary variables, and using the temporary variables in the conditional statement. For example, to map r1 to RAM, rewrite the previous code as follows:

  temp = mod(i,2);
  if (temp > 0)
      a = r1(u);
  else
      r1(i) = u;
  end 

• The persistent array or user-defined System object private property value depends on external inputs.

  For example, in the following code, bigarray does not map to RAM because it does not depend on u:

  function z = foo(u)
  
  persistent cnt bigarray
  if isempty(cnt)
      cnt = fi(0,1,16,10,hdlfimath);
      bigarray = uint8(zeros(1024,1));
  end
  z = u + cnt;
  idx = uint8(cnt);
  temp = bigarray(idx+1);
  cnt(:) = cnt + fi(1,1,16,0,hdlfimath) + temp;
  bigarray(idx+1) = idx; 

• RAMSize is greater than or equal to the RAMMappingThreshold value. RAMSize is the product NumElements * WordLength * Complexity.

  • NumElements is the number of elements in the array.

  • WordLength is the number of bits that represent the data type of the array.

  • Complexity is 2 for arrays with a complex base type; 1 otherwise.

If any of the above conditions is false, the persistent array or user-defined System object private property maps to a register in the HDL code.

RAMMappingThreshold

The default value of RAMMappingThreshold is 256. To change the threshold, use hdlset_param. For example, the following command changes the mapping threshold for the sfir_fixed model to 128 bits:

hdlset_param('sfir_fixed', 'RAMMappingThreshold', 128);

You can also change the RAM mapping threshold in the Configuration Parameters dialog box. For more information, see HDL Code Generation Pane: Global Settings.

Example

For an example that shows how to map persistent array variables to RAM in a MATLAB Function block, see RAM Mapping with the MATLAB Function Block.

OutputPipeline

OutputPipeline lets you specify a implementation with output pipelining for selected blocks. The parameter value specifies the number of output pipeline stages (pipeline depth) in the generated code.

The following code specifies an output pipeline depth of two stages for each Sum block in the model:

sblocks = find_system(gcb, 'BlockType', 'Sum');
for ii=1:length(sblocks),hdlset_param(sblocks{ii},'OutputPipeline', 2), end;

When generating code for pipeline registers, HDL Coder appends a postfix string to names of input or output pipeline registers. The default postfix string is _pipe. To customize the postfix string, use the Pipeline postfix option in the Configuration Parameters dialog box, in the HDL Code Generation > Global Settings > General tab. Alternatively, you can use the PipelinePostfix property with makehdl. See PipelinePostfix for an example.

See also Distributed Pipeline Insertion for MATLAB Function Blocks.

ResetType

Use the ResetType block parameter to suppress reset logic generation.

You can specify ResetType for the following blocks:

• Chart

• Convolutional Deinterleaver

• Convolutional Interleaver

• Delay

• Delay (DSP System Toolbox™)

• General Multiplexed Deinterleaver

• General Multiplexed Interleaver

• MATLAB Function

• MATLAB System

• Memory

• Tapped Delay

• Truth Table

• Unit Delay Enabled

• Unit Delay

Reset Logic for Optimizations in the MATLAB Function Block

When you set ResetType to none for a MATLAB Function block, HDL Coder does not generate reset logic for persistent variables in the MATLAB^® code.

However, if you specify other optimizations for the block, the coder may insert registers that use reset logic. The coder does not suppress reset logic generation for these registers. Therefore, if you set ResetType to none along with other block optimizations, your generated code may have a reset port at the top level.

How to Suppress Reset Logic Generation

To suppress reset logic generation for a block using the UI:

1. Right-click the block and select HDL Code > HDL Block Properties.

2. For ResetType, select none.

To suppress reset logic generation, on the command line, enter:

hdlset_param(path_to_block,'ResetType','none')

For example, to suppress reset logic generation for a Unit Delay block, UnitDelay1, within a subsystem, mySubsys, on the command line, enter:

hdlset_param('mySubsys/UnitDelay1','ResetType','none');

Specify Synchronous or Asynchronous Reset

To specify a synchronous or asynchronous reset, use the ResetType model-level parameter. For details, see ResetType.

SerialPartition

Use this parameter on Min/Max blocks to specify partitions for a serial cascade architecture. The default setting uses the minimum number of partitions.

This property is also used for serial filter architectures. For how to configure filter blocks, see SerialPartition.

SharingFactor

Use SharingFactor to specify the number of functionally equivalent resources to map to a single shared resource. The default is 0. See Resource Sharing.

SoftReset

Use the SoftReset block parameter to specify whether to generate hardware-friendly synchronous reset logic, or local reset logic that matches the Simulink simulation behavior. This property is available for the Unit Delay Resettable block or Unit Delay Enabled Resettable block.

When SoftReset set to 'off', the following code is generated for a Unit Delay Resettable block :

always @(posedge clk or posedge reset)
  begin : Unit_Delay_Resettable_process
    if (reset == 1'b1) begin
      Unit_Delay_Resettable_zero_delay <= 1'b1;
      Unit_Delay_Resettable_switch_delay <= 2'b00;
    end
    else begin
      if (enb) begin
        Unit_Delay_Resettable_zero_delay <= 1'b0;
        if (UDR_reset == 1'b1) begin
          Unit_Delay_Resettable_switch_delay <= 2'b00;
        end
        else begin
          Unit_Delay_Resettable_switch_delay <= In1;
        end
      end
    end
  end

assign Unit_Delay_Resettable_1 = 
            (UDR_reset || 
             Unit_Delay_Resettable_zero_delay ? 1'b1 : 1'b0);
assign out0 = (Unit_Delay_Resettable_1 == 1'b1 ? 2'b00 :
            Unit_Delay_Resettable_switch_delay);

When SoftReset set to 'on', the following code is generated for a Unit Delay Resettable block :

always @(posedge clk or posedge reset)
  begin : Unit_Delay_Resettable_process
    if (reset == 1'b1) begin
      Unit_Delay_Resettable_reg <= 2'b00;
    end
    else begin
      if (enb) begin
        if (UDR_reset != 1'b0) begin
          Unit_Delay_Resettable_reg <= 2'b00;
        end
        else begin
          Unit_Delay_Resettable_reg <= In1;
        end
      end
    end
  end

assign out0 = Unit_Delay_Resettable_reg;

StreamingFactor

Number of parallel data paths, or vectors, to transform into serial, scalar data paths by time-multiplexing serial data paths and sharing hardware resources. The default is 0, which implements fully parallel data paths. See also Streaming.

UseMatrixTypesInHDL

The UseMatrixTypesInHDL block property specifies whether to generate 2-D matrices in HDL code when you have MATLAB matrices in your MATLAB Function block.

To generate 2-D matrices in HDL code:

1. Right-click the MATLAB Function block and select HDL Code > HDL Block Properties.

2. For UseMatrixTypesInHDL, select on.

Alternatively, at the command line, use makehdl or hdlset_param to set the UseMatrixTypesInHDL block property to 'on'.

For example, suppose you have a model, myModel, with a subsystem, dutSubsys, that contains a MATLAB Function block, myMLFcn. To generate 2-D matrices in HDL code for myMLFcn, enter:

hdlset_param('myModel/dutSubsys/myMLFcn', 'UseMatrixTypesInHDL', 'on')

UseRAM

The UseRAM implementation parameter enables using RAM-based mapping for a block instead of mapping to a shift register.

This implementation parameter is available for the Delay block in the Simulink Discrete library and the Delay block in the DSP System Toolbox Signal Operations library.

Mapping Multiple Delays to RAM

HDL Coder can also merge several delays of equal length into one delay and then map the merged delay to a single RAM. This optimization provides the following benefits:

• Increased occupancy on a single RAM

• Sharing of address generation logic, which minimizes duplication of identical HDL code

• Mapping of delays to a RAM when the individual delays do not satisfy the threshold

The following rules control whether or not multiple delays can merge into one delay:

• The delays must:

  • Be at the same level of the subsystem hierarchy.

  • Use the same compiled sample time.

  • Have UseRAM set to on, or be generated by streaming or resource sharing.

  • Have the same ResetType setting, which cannot be none.

• The total word length of the merged delay cannot exceed 128 bits.

• The RAMSize of the merged delay is greater than or equal to the RAMMappingThreshold value. RAMSize is the product DelayLength * WordLength * VectorLength * ComplexLength.

  • DelayLength is the total number of delays.

  • WordLength is the number of bits that represent the data type of the merged delay.

  • VectorLength is the number of elements in a vector delay. VectorLength is 1 for a scalar delay.

  • ComplexLength is 2 for complex delays; 1 otherwise.

Example of Multiple Delays Mapping to a Block RAM

RAMMappingThreshold for the following model is 100 bits.

The Delay and Delay1 blocks merge and map to a dual-port RAM in the generated HDL code by satisfying the following conditions:

• Both delay blocks:

  • Are at the same level of the hierarchy.

  • Use the same compiled sample time.

  • Have UseRAM set to on in the HDL block properties dialog box.

  • Have the same ResetType setting of default.

• The total word length of the merged delay is 28 bits, which is below the 128-bit limit.

• The RAMSize of the merged delay is 112 bits (4 delays * 28-bit word length), which is greater than the mapping threshold of 100 bits.

When you generate HDL code for this model, HDL Coder generates additional files to specify RAM mapping. The coder stores these files in the same source location as other generated HDL files, for example, the hdlsrc folder.

Effects of Streaming and Distributed Pipelining

When UseRAM is off for a Delay block, HDL Coder maps the delay to a shift register by default. However, the coder changes the UseRAM setting to on and tries to map the delay to a RAM under the following conditions:

• Streaming is enabled for the subsystem with the Delay block.

• Distributed pipelining is disabled for the subsystem with the Delay block.

Suppose that distributed pipelining is enabled for the subsystem with the Delay block.

• When UseRAM is off, the Delay block participates in retiming.

• When UseRAM is on, the Delay block does not participate in retiming. HDL Coder does not break up a delay marked for RAM mapping.

  Consider a subsystem with two Delay blocks, three Constant blocks, and three Product blocks:

  

  When UseRAM is on for the Delay block on the right, that delay does not participate in retiming.

The following summary describes whether or not HDL Coder tries to map a delay to a RAM instead of a shift register.

VariablesToPipeline

Warning   VariablesToPipeline is not recommended. Use coder.hdl.pipeline instead.

The VariablesToPipeline parameter enables you to insert a pipeline register at the output of one or more MATLAB variables. Specify a list of variables as a character vector, with spaces separating the variables.

See also Pipeline MATLAB Expressions.