Specify VHDL coding style used to detect clock transitions
'on'
Selected
Generated code uses the VHDL® rising_edge or falling_edge function
to detect clock transitions.
For example, the following code, generated from a Unit Delay
block, uses rising_edge to detect positive clock
transitions:
Unit_Delay1_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Unit_Delay1_out1 <= (OTHERS => '0');
ELSIF rising_edge(clk) THEN
IF clk_enable = '1' THEN
Unit_Delay1_out1 <= signed(x_in);
END IF;
END IF;
END PROCESS Unit_Delay1_process;
'off' (default)
Cleared (default)
Generated code uses the 'event syntax.
For example, the following code, generated from a Unit Delay
block, uses clk'event AND clk = '1' to detect positive
clock transitions:
Unit_Delay1_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Unit_Delay1_out1 <= (OTHERS => '0');
ELSIF clk'event AND clk = '1' THEN
IF clk_enable = '1' THEN
Unit_Delay1_out1 <= signed(x_in);
END IF;
END IF;
END PROCESS Unit_Delay1_process;
To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.