Settings

'on'

Generate target-independent HDL code from single-precision floating-point models. You can deploy the generated code on any generic FPGA or ASIC.

When you have Single data types in your design, select this option.

'off' (default)

Do not use native floating-point for HDL code generation.

Usage Example

Use this property with makehdl. For example, to generate code from the sfir_fixed/symmetric_fir subsystem, enter:

makehdl ('sfir_fixed/symmetric_sfir','NativeFloatingPoint','on')

See Also

• HDL Coder Native Floating-Point Support

• Generate Target-Independent HDL Code with Native Floating-Point