TestBenchClockEnableDelay
Define elapsed time in clock cycles between deassertion of reset and assertion of clock enable
Settings
N (integer number
of clock cycles)
Default: 1
The TestBenchClockEnableDelay property
specifies a delay time N, expressed in
base-rate clock cycles ( the default value is 1) elapsed between the
time the reset signal is deasserted and the time the clock enable
signal is first asserted. TestBenchClockEnableDelay
works in conjunction with the HoldTime property;
after deassertion of reset, the clock enable goes high after a delay
of N base-rate clock cycles plus the delay
specified by HoldTime.
In the figure below, the reset signal (active-high) deasserts
after the interval labelled Hold Time. The clock
enable asserts after a further interval labelled Clock enable
delay.
Set or View This Property
To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.