HDL Workflow Command Line Interface

End-to-end scripting for generic ASIC/FPGA, FPGA Turnkey, and IP core generation workflows

Classes

hdlcoder.WorkflowConfig Configure HDL code generation and deployment workflows

`hdlcoder.runWorkflow`	Run HDL code generation and deployment workflow
`hdlcoder.WorkflowConfig.export`	Generate MATLAB script that recreates the workflow configuration
`hdlcoder.WorkflowConfig.setAllTasks`	Enable all tasks in workflow
`hdlcoder.WorkflowConfig.clearAllTasks`	Disable all tasks in workflow
`hdlcoder.WorkflowConfig.validate`	Check property values in HDL Workflow CLI configuration object

SynthesisProjectAdditionalFiles	Include additional HDL or constraint files in synthesis project
SynthesisTool	Specify synthesis tool
SynthesisToolChipFamily	Specify target device chip family name
SynthesisToolDeviceName	Specify target device name
SynthesisToolPackageName	Specify target device package name
SynthesisToolSpeedValue	Specify target device speed value

Inport	Create input port for subsystem or external input (HDL Coder)
Outport	Create output port for subsystem or external output (HDL Coder)

Export, import, or configure an HDL Workflow CLI command script

Tool-specific Tcl commands that correspond to the HDL Workflow synthesis objectives

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