Settings

'Enable input port'

Default: 'clk_enable'

Specify the name for the model's clock enable input port as a character vector.

If you override the default with (for example) 'filter_clock_enable' for the generating subsystem filter_subsys, the generated entity declaration might look as follows:

ENTITY filter_subsys IS
   PORT( clk                 :  IN  std_logic;
         filter_clock_enable :  IN  std_logic;
         reset               :  IN  std_logic;
         filter_subsys_in    :  IN  std_logic_vector (15 DOWNTO 0);
         filter_subsys_out   :  OUT std_logic_vector (15 DOWNTO 0);
         );
END filter_subsys;

If you specify a VHDL^® or Verilog^® reserved word, the code generator appends a reserved word postfix string to form a valid VHDL or Verilog identifier. For example, if you specify the reserved word signal, the resulting name string would be signal_rsvd. See ReservedWordPostfix for more information.

Usage Notes

The clock enable signal is asserted active high (1). Thus, the input value must be high for the generated entity's registers to be updated.

Set or View This Property

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

ClockInputPort, InputType, OutputType, ResetInputPort