Settings

'Reset input'

Default: 'reset'.

Specify the name for the model's reset input port as a character vector.

For example, if you override the default with 'chip_reset' for the generating system myfilter, the generated entity declaration might look as follows:

ENTITY myfilter IS
   PORT( clk             :  IN  std_logic;
         clk_enable      :  IN  std_logic;
         chip_reset      :  IN  std_logic;
         myfilter_in     :  IN  std_logic_vector (15 DOWNTO 0); 
         myfilter_out    :  OUT std_logic_vector (15 DOWNTO 0); 
         );
END myfilter;

If you specify a VHDL^® or Verilog^® reserved word, the code generator appends a reserved word postfix string to form a valid VHDL or Verilog identifier. For example, if you specify the reserved word signal, the resulting name string would be signal_rsvd. See ReservedWordPostfix for more information.

Usage Notes

If the reset asserted level is set to active high, the reset input signal is asserted active high (1) and the input value must be high (1) for the entity's registers to be reset. If the reset asserted level is set to active low, the reset input signal is asserted active low (0) and the input value must be low (0) for the entity's registers to be reset.

Set or View This Property

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

ClockEnableInputPort, InputType, OutputType