Settings

'on'

For triggered subsystems, use the trigger input signal as a clock in the generated HDL code.

'off' (default)

For triggered subsystems, do not use the trigger input signal as a clock in the generated HDL code.

Usage Example

Use hdlset_param or makehdl to set this property.

For example, to generate HDL code that uses the trigger signal as clock for triggered subsystems within the sfir_fixed/symmetric_fir DUT subsystem, enter:

makehdl ('sfir_fixed/symmetric_sfir','TriggerAsClock','on')

Set or View This Property

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

More About

• Use Trigger As Clock in Triggered Subsystems