Optimize timing controller entity by implementing separate counters per rate
'on' (default)
A timing controller code file is generated if required by the design, for example:
When code is generated for a multirate model.
When a cascade block implementation for certain blocks is specified.
This file contains a module defining timing signals (clock, reset, external clock enable inputs and clock enable output) in a separate entity or module. In a multirate model, the timing controller entity generates the required rates from a single master clock using one or more counters and multiple clock enables.
When OptimizeTimingController is set 'on' (the
default), HDL Coder™ generates multiple counters (one counter for
each rate in the model). The benefit of this optimization is that
it generates faster logic, and the size of the generated code is usually
much smaller.
'off'
When OptimizeTimingController is set 'off',
the timing controller uses one counter to generate the rates in the
model.
To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.