Use compiler `timescale directives
in generated Verilog code
'on' (default)
Selected (default)
Use compiler `timescale directives in generated Verilog® code.
'off'
Cleared
Suppress the use of compiler `timescale directives
in generated Verilog code.
The `timescale directive provides a way of
specifying different delay values for multiple modules in a Verilog file.
This setting does not affect the generated
test bench.
To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.