Specify whether VHDL FOR and GENERATE loops
are unrolled and omitted from generated VHDL code
'on'
Selected
Unroll and omit FOR and GENERATE loops
from the generated VHDL® code.
In Verilog® code, loops are always unrolled.
If you are using an electronic design automation (EDA) tool
that does not support GENERATE loops, you can enable
this option to omit loops from your generated VHDL code.
'off' (default)
Cleared (default)
Include FOR and GENERATE loops
in the generated VHDL code.
The setting of this option does not affect results obtained from simulation or synthesis of generated VHDL code.
To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.