Settings

'Rising' (default)

The rising clock edge triggers Verilog^® always or VHDL^® process blocks in the generated code.

'Falling'

The falling clock edge triggers Verilog always or VHDL process blocks in the generated code.

Set or View This Property

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

ResetAssertedLevel, ClockInputPort, InputType, OutputType, ResetInputPort