Settings

'on'

Omit generation of clock enable logic for single-rate designs, wherever possible (see Usage Notes). The following VHDL^® code example does not define or examine a clock enable signal. When the clock signal (clk) goes high, the current signal value is output.

Unit_Delay_process : PROCESS (clk, reset)
  BEGIN
    IF reset = '1' THEN
      Unit_Delay_out1 <= to_signed(0, 32);
    ELSIF clk'EVENT AND clk = '1' THEN
      Unit_Delay_out1 <= In1_signed;
    END IF;
  END PROCESS Unit_Delay_process;

'off' (default)

Generate clock enable logic. The following VHDL code extract represents a register with a clock enable (enb)

Unit_Delay_process : PROCESS (clk, reset)
  BEGIN
    IF reset = '1' THEN
      Unit_Delay_out1 <= to_signed(0, 32);
    ELSIF clk'EVENT AND clk = '1' THEN
      IF enb = '1' THEN
        Unit_Delay_out1 <= In1_signed;
      END IF;
    END IF;
  END PROCESS Unit_Delay_process;

Usage Notes

In some cases, HDL Coder™ emits clock enables even when MinimizeClockEnables is 'on'. These cases are:

• Registers inside Enabled, State-Enabled, and Triggered subsystems.

• Multirate models.

• The coder emits clock enables for the following blocks:

  • commseqgen2/PN Sequence Generator

  • dspsigops/NCO

    Note:   HDL support for the NCO block will be removed in a future release. Use the NCO HDL Optimized block instead.

  • dspsrcs4/Sine Wave

  • hdldemolib/HDL FFT

  • built-in/DiscreteFir

  • dspmlti4/CIC Decimation

  • dspmlti4/CIC Interpolation

  • dspmlti4/FIR Decimation

  • dspmlti4/FIR Interpolation

  • dspadpt3/LMS Filter

  • dsparch4/Biquad Filter

Set or View This Property

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.