Settings

'on'

Selected

Generate VHDL^® code for model references into a single library.

'off' (default)

Cleared (default)

For each model reference, generate a separate VHDL library.

Note:   This property is specific to VHDL code generation. It does not apply to Verilog® code generation and should not be enabled when generating Verilog code.

Set or View This Property

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

VHDLLibraryName