MultifileTestBench

Divide generated test bench into helper functions, data, and HDL test bench code files

Settings

'on'

Write separate files for test bench code, helper functions, and test bench data. The file names are derived from the name of the DUT, the TestBenchPostfix property, and the TestBenchDataPostfix property as follows:

DUTname_TestBenchPostfix_TestBenchDataPostfix

For example, if the DUT name is symmetric_fir, and the target language is VHDL®, the default test bench file names are:

  • symmetric_fir_tb.vhd: test bench code

  • symmetric_fir_tb_pkg.vhd: helper functions package

  • symmetric_fir_tb_data.vhd: data package

If the DUT name is symmetric_fir and the target language is Verilog®, the default test bench file names are:

  • symmetric_fir_tb.v: test bench code

  • symmetric_fir_tb_pkg.v: helper functions package

  • symmetric_fir_tb_data.v: test bench data

'off' (default)

Write a single test bench file containing the HDL test bench code and helper functions and test bench data.

Set or View This Property

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

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