Enable this property to optimize Delay blocks with non zero initial condition
'on' (default)
Transform Delay blocks with nonzero Initial condition in your Simulink® model to Delay blocks with zero Initial condition and some additional logic in the generated HDL code.
By using this transformation, HDL Coder™ can perform optimizations such as sharing, distributed pipelining, and clock-rate pipelining more effectively, and prevent an assertion from being triggered in the validation model.
'off'
Do not transform Delay blocks with nonzero Initial condition in your Simulink model.
Use hdlset_param or makehdl to
set this property.
For example, if you do not want to transform Delay blocks
with nonzero Initial condition within the sfir_fixed/symmetric_fir subsystem,
enter:
makehdl ('sfir_fixed/symmetric_sfir','TransformNonZeroInitDelay','off')To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.