Settings

'on'

Write the generated VHDL^® code to a single file.

'off'(default)

Write the code for the generated VHDL entity and architecture to separate files.

The names of the entity and architecture files derive from the base file name (as specified by the generating model or subsystem name). By default, postfix strings identifying the file as an entity (_entity) or architecture (_arch ) are appended to the base file name. You can override the default and specify the postfix as a character vector.

For example, instead of all generated code residing in MyFIR.vhd, you can specify that the code reside in MyFIR_entity.vhd and MyFIR_arch.vhd.

Note:   This property is specific to VHDL code generation. It does not apply to Verilog® code generation and should not be enabled when generating Verilog code.

Set or View This Property

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

SplitArchFilePostfix, SplitEntityFilePostfix