HDL Code Generation from a Simulink Model

Before You Generate Code

Before you generate HDL code from your own models, you should do the following:

Before generating code, use the hdlsetup utility (described in Initializing Model Parameters with hdlsetup) to set up your model for HDL code generation quickly and consistently.
Use the hdllib utility to create a library of blocks that are currently supported for HDL code generation, as described in Show Blocks Supported for HDL Code Generation. By constructing models with blocks from this library, your models will be HDL compatible.
The set of supported blocks will change in future releases, so you should rebuild your supported blocks library each time you install a new version of this product.
Use the Run Compatibility Checker option (described in Selecting and Checking a Subsystem for HDL Compatibility) to check HDL compatibility of your model or DUT and generate an HDL Code Generation Check Report.
Alternatively, you can invoke the checkhdl function (see checkhdl) to run the compatibility checker.

Overview of Exercises

HDL Coder™ supports HDL code generation in your choice of environments:

The MATLAB^® Command Window supports code generation using the makehdl, makehdltb, and other functions.
The Simulink^® GUI (the Configuration Parameters dialog box and/or Model Explorer) provides an integrated view of the model simulation parameters and HDL code generation parameters and functions.

The hands-on exercises in this chapter introduce you to the mechanics of generating and simulating HDL code, using the same model to generate code in both environments. In a series of steps, you will

Configure a simple model for code generation.
Generate VHDL^® code from a subsystem of the model.
Generate a VHDL test bench and scripts for the Mentor Graphics^® ModelSim^® simulator to drive a simulation of the model.
Compile and execute the model and test bench code in the simulator.
Generate and simulate Verilog^® code from the same model.
Check a model for compatibility with HDL Coder.

The sfir_fixed Model

These exercises use the sfir_fixed model as a source for HDL code generation. The model simulates a symmetric finite impulse response (FIR) filter algorithm, implemented with fixed-point arithmetic.

The blocks in this example model support HDL code generation, and the model parameters have been configured for HDL code generation. To learn more about preparing your model for code generation, see Prepare Simulink Model For HDL Code Generation.

The following figure shows the top level of the model.

This model uses a division of labor that is helpful in HDL design:

The symmetric_fir subsystem, which implements the filter algorithm, is the device under test (DUT). An HDL entity will be generated, tested, and eventually synthesized from this subsystem.
The top-level model components that drive the subsystem work as a test bench.

The top-level model generates 16-bit fixed-point input signals for the symmetric_fir subsystem. The Signal From Workspace block generates a test input (stimulus) signal for the filter. The four Constant blocks provide filter coefficients.

The Scope blocks are used in simulation only. They are virtual blocks, and do not generate HDL code.

The following figure shows the symmetric_fir subsystem.

The fixed-point data types propagate through the subsystem. Inputs inherit the data types of the signals presented to them. Where required, internal rules of the blocks determine the output data type, given the input data types and the operation performed (for example, the Product blocks).

The filter outputs a fixed-point result at the y_out port, and also replicates its input (after passing it through several delay stages) at the delayed_x_out port.

In the exercises that follow, you generate VHDL code that implements the symmetric_fir subsystem as an entity. You then generate a test bench from the top-level model. The test bench drives the generated entity, for the required number of clock steps, with stimulus data generated from the Signal From Workspace block.

Generate Code Using the HDL Workflow Advisor

This example shows how to generate HDL code from a Simulink model using the HDL Workflow Advisor.

The model you use in this example, sfir_fixed, is already prepared for code generation.

This example uses the Xilinx^® ISE synthesis tool, and assumes your synthesis tool path is set up. You can also follow this example using Altera^® Quartus II.

Create Working Folder and Copy Model
Generate Code Using the HDL Workflow Advisor
Perform FPGA Synthesis and Analysis

Create Working Folder and Copy Model

Start MATLAB.
Create a folder named sl_hdlcoder_work. For example:
```
mkdir C:\work\sl_hdlcoder_work
```
You will use sl_hdlcoder_work to store a local copy of the example model and to store folders and code generated by HDL Coder. The location of the folder does not matter, except that it should not be within the MATLAB folder tree.
Make the sl_hdlcoder_work folder your working folder. For example:
```
cd C:\work\sl_hdlcoder_work
```
Open the sfir_fixed model.
```
sfir_fixed
```
Save a copy of sfir_fixed in your sl_hdlcoder_work folder.

Generate Code Using the HDL Workflow Advisor

Right-click the symmetric_fir subsystem and select HDL Code > HDL Workflow Advisor.
In the Set Target > Set Target Device and Synthesis Tool step, for Synthesis tool, select Xilinx ISE and click Run This Task.
Right-click Prepare Model For HDL Code Generation and select Run All. The HDL Workflow Advisor checks the model for code generation compatibility.
In the HDL Code Generation > Set Code Generation Options > Set Basic Options step, select the following options, then click Apply:
- For Language, select Verilog.
- Enable Generate traceability report.
- Enable Generate resource utilization report.
View the options available in the Optimization and Coding style tabs. You can use these options to modify the implementation and format of the generated code.
Right-click the HDL Code Generation > Generate RTL Code and Testbench step, and select Run to Selected Task.
The code generation report, which includes the resource utilization and traceability reports, opens automatically. The resource utilization report shows the hardware resources your design implementation is using. The traceability report enables you to navigate between your model and the generated code.

Perform FPGA Synthesis and Analysis

In the FPGA Synthesis and Analysis > Perform Synthesis and P/R > Perform Place and Route task, unselect Skip this task and click Apply.
Right-click Annotate Model with Synthesis Result and select Run to Selected Task.
View the annotated critical path in the model.
The critical path is colored cyan.

Generate HDL Code Using the Command Line

Overview
Creating a Folder and Local Model File
Initializing Model Parameters with hdlsetup
Generating a VHDL Entity from a Subsystem
Generating VHDL Test Bench Code
Verifying Generated Code
Generating a Verilog Module and Test Bench

Overview

This exercise provides a step-by-step introduction to code and test bench generation commands, their arguments, and the files created by the code generator. The exercise assumes that you have familiarized yourself with the example model (see The sfir_fixed Model).

Creating a Folder and Local Model File

Make a local copy of the example model and store it in a working folder, as follows.

Start the MATLAB software.
Create a folder named sl_hdlcoder_work, for example:
```
mkdir C:\work\sl_hdlcoder_work
```
The sl_hdlcoder_work folder will store a local copy of the example model and to store folders and code generated by HDL Coder. The location of the folder does not matter, except that it should not be within the MATLAB tree.
Make the sl_hdlcoder_work folder your working folder, for example:
```
cd C:\work\sl_hdlcoder_work
```
To open the example model, type the following command at the MATLAB prompt:
```
sfir_fixed
```
In Simulink, select File > Save As and save a local copy of the sfir_fixed model to your working folder.
Leave the sfir_fixed model open and proceed to the next section.

Initializing Model Parameters with hdlsetup

Before generating code, you must configure the model. You can use the hdlsetup command instead of configuring the model manually. The hdlsetup command uses the set_param function to set up models for HDL code generation quickly and consistently.

To configure the model for HDL code generation:

At the MATLAB command prompt, enter:
```
hdlsetup('sfir_fixed')
```
Select Save from the File menu, to save the model with its new settings.

Before continuing with code generation, consider the settings that hdlsetup applies to the model.

hdlsetup configures the Solver options that are recommended or required by HDL Coder. These are

Type: Fixed-step. (HDL Coder currently supports variable-step solvers under limited conditions. See hdlsetup)
Solver: Discrete (no continuous states). Other fixed-step solvers could be selected, but this option is usually the best one for simulating discrete systems.
Tasking mode: SingleTasking. HDL Coder does not currently support models that execute in multitasking mode.
Do not set Tasking mode to Auto.

hdlsetup also configures the model start and stop times and fixed-step size as follows:

Start Time: 0.0 s
Stop Time: 10 s
Fixed step size (fundamental periodic sample time) : auto

If Fixed step size is set to auto the step size is chosen automatically, based on the sample times specified in the model. In the example model, only the Signal From Workspace block specifies an explicit sample time (1 s); the other blocks inherit this sample time.

The model start and stop times determine the total simulation time. This in turn determines the size of data arrays that are generated to provide stimulus and output data for generated test benches. For the example model, computation of 10 seconds of test data does not take a significant amount of time. Computation of sample values for more complex models can be time consuming. In such cases, you may want to decrease the total simulation time.

The remaining parameters set by hdlsetup control error severity levels, data logging, and model display options. If you want to view the complete set of model parameters affected by hdlsetup, open hdlsetup.m in the MATLAB Editor.

The model parameter settings provided by are intended as useful defaults, but they may not be optimal for your application. For example, hdlsetup sets a default Simulation stop time of 10 s. A total simulation time of 1000 s would be more realistic for a test of the sfir_fixed example model. If you would like to change the simulation time, enter the desired value into the Simulation stop time field of the Simulink window.

See the "Model Parameters" table in the "Model and Block Parameters" section of the Simulink documentation for a summary of model parameters.

Generating a VHDL Entity from a Subsystem

In this section, you will use the makehdl function to generate code for a VHDL entity from the symmetric_fir subsystem of the example model. makehdl also generates script files for third-party HDL simulation and synthesis tools.

makehdl lets you specify numerous properties that control various features of the generated code. In this example, you will use the makehdl property defaults.

Before generating code, make sure that you have completed the steps described in Creating a Folder and Local Model File and Initializing Model Parameters with hdlsetup.

To generate code:

Select Current Folder from the Desktop menu in the MATLAB window. This displays the MATLAB Current Folder browser, which lets you easily access your working folder and the files that will be generated within it.
At the MATLAB prompt, type the command
```
makehdl('sfir_fixed/symmetric_fir')
```
This command directs HDL Coder to generate code from the symmetric_fir subsystem within the sfir_fixed model, using default property values.
As code generation proceeds, HDL Coder displays progress messages. The process should complete with the message
```
### HDL Code Generation Complete.
```
Observe that the names of generated files in the progress messages are hyperlinked. After code generation completes, you can click these hyperlinks to view the files in the MATLAB Editor.
makehdl compiles the model before generating code. Depending on model display options (such as port data types, etc.), the appearance of the model may change after code generation.
By default, makehdl generates VHDL code. Code files and scripts are written to a target folder. The default target folder is a subfolder of your working folder, named hdlsrc.
A folder icon for the hdlsrc folder is now visible in the Current Folder browser. To view generated code and script files, double-click the hdlsrc folder icon.
The files that makehdl has generated in the hdlsrc folder are
- symmetric_fir.vhd: VHDL code. This file contains an entity definition and RTL architecture implementing the symmetric_fir filter.
- symmetric_fir_compile.do: Mentor Graphics ModelSim compilation script (vcom command) to compile the generated VHDL code.
- symmetric_fir_synplify.tcl: Synplify^® synthesis script
- symmetric_fir_map.txt: Mapping file. This report file maps generated entities (or modules) to the subsystems that generated them (see Trace Code Using the Mapping File).
To view the generated VHDL code in the MATLAB Editor, double-click the symmetric_fir.vhd file icon in the Current Folder browser.
Before proceeding to the next section, close files you have opened in the editor. Then, click the Go Up One Level button in the Current Folder browser, to set the current folder back to your sl_hdlcoder_work folder.
Leave the sfir_fixed model open and proceed to the next section.

Generating VHDL Test Bench Code

In this section, you use the test bench generation function, makehdltb, to generate a VHDL test bench. The test bench is designed to drive and verify the operation of the symmetric_fir entity that was generated in the previous section. A generated test bench includes

Stimulus data generated by signal sources connected to the entity under test.
Output data generated by the entity under test. During a test bench run, this data is compared to the outputs of the VHDL model, for verification purposes.
Clock, reset, and clock enable inputs to drive the entity under test.
A component instantiation of the entity under test.
Code to drive the entity under test and compare its outputs to the expected data.

In addition, makehdltb generates Mentor Graphics ModelSim scripts to compile and execute the test bench.

This exercise assumes that your working folder is the same as that used in the previous section. This folder now contains an hdlsrc folder containing the previously generated code.

To generate a test bench:

At the MATLAB prompt, type the command
```
makehdltb('sfir_fixed/symmetric_fir')
```
This command generates a test bench that is designed to interface to and validate code generated from symmetric_fir (or from a subsystem with a functionally identical interface). By default, VHDL test bench code, as well as scripts, are generated in the hdlsrc target folder.
As test bench generation proceeds, HDL Coder displays progress messages. The process should complete with the message
```
### HDL TestBench Generation Complete.
```
To view generated test bench and script files, double-click the hdlsrc folder icon in the Current Folder browser. Alternatively, you can click the hyperlinked names of generated files in the code test bench generation progress messages.
The files generated by makehdltb are:
- symmetric_fir_tb.vhd: VHDL test bench code and generated test and output data.
- symmetric_fir_tb_compile.do: Mentor Graphics ModelSim compilation script (vcom commands). This script compiles and loads both the entity to be tested (symmetric_fir.vhd) and the test bench code (symmetric_fir_tb.vhd).
- symmetric_fir_tb_sim.do: Mentor Graphics ModelSim script to initialize the simulator, set up wave window signal displays, and run a simulation.
If you want to view the generated test bench code in the MATLAB Editor, double-click the symmetric_fir.vhd file icon in the Current Folder browser. You may want to study the code while referring to the makehdltb reference documentation, which describes the default actions of the test bench generator.
Before proceeding to the next section, close files you have opened in the editor. Then, click the Go Up One Level button in the Current Folder browser, to set the current folder back to your sl_hdlcoder_work folder.

Verifying Generated Code

You can now take the previously generated code and test bench to an HDL simulator for simulated execution and verification of results. See Simulating and Verifying Generated HDL Code for an example of how to use generated test bench and script files with the Mentor Graphics ModelSim simulator.

Generating a Verilog Module and Test Bench

The procedures for generating Verilog code differ only slightly from those for generating VHDL code. This section provides an overview of the command syntax and the generated files.

Generating a Verilog Module. By default, makehdl generates VHDL code. To override the default and generate Verilog code, you must pass in a property/value pair to makehdl, setting the TargetLanguage property to 'verilog', as in this example.

makehdl('sfir_fixed/symmetric_fir','TargetLanguage','verilog')

The previous command generates Verilog source code, as well as scripts for the simulation and the synthesis tools, in the default target folder, hdlsrc.

The generated files are:

symmetric_fir.v: Verilog code. This file contains a Verilog module implementing the symmetric_fir subsystem.
symmetric_fir_compile.do: Mentor Graphics ModelSim compilation script (vlog command) to compile the generated Verilog code.
symmetric_fir_synplify.tcl: Synplify synthesis script.
symmetric_fir_map.txt: Mapping file. This report file maps generated entities (or modules) to the subsystems that generated them (see Trace Code Using the Mapping File).

Generating and Executing a Verilog Test Bench. The makehdltb syntax for overriding the target language is exactly the same as that for makehdl. The following example generates Verilog test bench code to drive the Verilog module, symmetric_fir, in the default target folder.

makehdltb('sfir_fixed/symmetric_fir','TargetLanguage','verilog')

The generated files are:

symmetric_fir_tb.v: Verilog test bench code and generated test and output data.
symmetric_fir_tb_compile.do: Mentor Graphics ModelSim compilation script (vlog commands). This script compiles and loads both the entity to be tested (symmetric_fir.v) and the test bench code (symmetric_fir_tb.v).
symmetric_fir_tb_sim.do: Mentor Graphics ModelSim script to initialize the simulator, set up wave window signal displays, and run a simulation.

The following listing shows the commands and responses from a test bench session using the generated scripts:

ModelSim> do symmetric_fir_tb_compile.do
# Model Technology ModelSim SE vlog 6.0 Compiler 2004.08 Aug 19 2004
# -- Compiling module symmetric_fir
# 
# Top level modules:
# 	symmetric_fir
# Model Technology ModelSim SE vlog 6.0 Compiler 2004.08 Aug 19 2004
# -- Compiling module symmetric_fir_tb
# 
# Top level modules:
# 	symmetric_fir_tb
ModelSim>do symmetric_fir_tb_sim.do
# vsim work.symmetric_fir_tb 
# Loading work.symmetric_fir_tb
# Loading work.symmetric_fir
# **** Test Complete. ****
# Break at 
C:/work/sl_hdlcoder_work/vlog_code/symmetric_fir_tb.v line 142
# Simulation Breakpoint:Break at
C:/work/sl_hdlcoder_work/vlog_code/symmetric_fir_tb.v line 142
# MACRO ./symmetric_fir_tb_sim.do PAUSED at line 14

Generate HDL Code Using the Configuration Parameters Dialog Box

HDL Coder GUI Overview
Creating a Folder and Local Model File
Viewing Coder Options in the Configuration Parameters Dialog Box
Initializing Model Parameters with hdlsetup
Selecting and Checking a Subsystem for HDL Compatibility
Generating VHDL Code
Generating VHDL Test Bench Code
Verifying Generated Code
Generating Verilog Model and Test Bench Code

HDL Coder GUI Overview

You can view and edit options and parameters that affect HDL code generation in the Configuration Parameters dialog box, or in the Model Explorer.

The following figure shows the top-level HDL Code Generation pane in the Configuration Parameters dialog box.

The following figure shows the top-level HDL Code Generation options pane in the Model Explorer.

In the code generation exercises that follow, you use the Configuration Parameters dialog box to view and set HDL Coder options and controls. The exercises use the sfir_fixed model (see The sfir_fixed Model) in basic code generation and verification steps.

Creating a Folder and Local Model File

In this section you will setup the folder and a local copy of the example model.

Creating a Folder. Start by setting up a working folder:

Start MATLAB.
Create a folder named sl_hdlcoder_work, for example:
```
mkdir C:\work\sl_hdlcoder_work
```
You will use sl_hdlcoder_work to store a local copy of the example model and to store folders and code generated by HDL Coder. The location of the folder does not matter, except that it should not be within the MATLAB folder tree.
Make the sl_hdlcoder_work folder your working folder, for example:
```
cd C:\work\sl_hdlcoder_work
```

Making a Local Copy of the Model File. Next, make a copy of the sfir_fixed model:

To open the model, type the following command at the MATLAB prompt:
```
sfir_fixed
```
Save a local copy of the sfir_fixed model to your working folder.
Leave the sfir_fixed model open and proceed to the next section.

Viewing Coder Options in the Configuration Parameters Dialog Box

HDL Coder option settings are displayed as a category of the model's active configuration set. You can view and edit these options in the Configuration Parameters dialog box, or in the Model Explorer. This discussion uses the Configuration Parameters dialog box.

To access HDL Coder settings:

Open the Configuration Parameters dialog box.
Select the HDL Code Generation pane.

The HDL Code Generation pane contains top-level options and buttons that control the HDL code generation process. Several other categories of options are available under the HDL Code entry. This exercise uses a small subset of these options, leaving the others at their default settings.

Initializing Model Parameters with hdlsetup

Before generating code, you must set some parameters of the model. Rather than doing this manually, use the hdlsetup command. The hdlsetup command uses the set_param function to set up models for HDL code generation quickly and consistently.

To set the model parameters:

At the MATLAB command prompt, type:
```
hdlsetup('sfir_fixed')
```
Save the model with its new settings.

Before continuing with code generation, consider the settings that hdlsetup applies to the model.

hdlsetup configures Solver options that are recommended or required by HDL Coder. These options are:

Type: Fixed-step. (HDL Coder currently supports variable-step solvers under limited conditions. See hdlsetup.)
Solver: Discrete (no continuous states). Other fixed-step solvers could be selected, but this option is usually the best one for simulating discrete systems.
Tasking mode: SingleTasking. HDL Coder does not currently support models that execute in multitasking mode.
Do not set Tasking mode to Auto.

hdlsetup also configures the model start and stop times and fixed-step size as follows:

Start Time: 0.0 s
Stop Time: 10 s
Fixed step size (fundamental periodic sample time): auto

The model parameter settings provided by hdlsetup are intended as useful defaults, but they may not be optimal for your application. For example, hdlsetup sets a default Simulation stop time of 10 s. A total simulation time of 1000 s would be more realistic for a test of the sfir_fixed example model. If you would like to change the simulation time, enter the desired value into the Simulation stop time field of the Simulink Editor.

See the "Model Parameters" table in the "Model and Block Parameters" section of the Simulink documentation for a summary of model parameters.

Selecting and Checking a Subsystem for HDL Compatibility

HDL Coder generates code from either the current model or from a subsystem at the root level of the current model. You use the Generate HDL for menu to select the model or subsystem from which code is to be generated. Each entry in the menu shows the full path to the model or one of its subcomponents.

The sfir_fixed model is configured with the sfir_fixed/symmetric_fir subsystem selected for code generation. If this is not the case, make sure that the symmetric_fir subsystem is selected for code generation, as follows:

Select sfir_fixed/symmetric_fir from the Generate HDL for menu.
Click Apply.

To check HDL compatibility for the subsystem:

Click the Run Compatibility Checker button.
The HDL compatibility checker examines the system selected in the Generate HDL for menu for compatibility problems. In this case, the selected subsystem is fully HDL-compatible, and the compatibility checker displays the following message:
```
### Starting HDL Check.
### HDL Check Complete with 0 errors, warnings and messages.
```
The compatibility checker also displays a report in a new window.

Generating VHDL Code

The top-level HDL Code Generation options are now set as follows:

The Generate HDL for field specifies the sfir_fixed/symmetric_fir subsystem for code generation.
The Language field specifies (by default) generation of VHDL code.
The Folder field specifies a target folder that stores generated code files and scripts. The default target folder is a subfolder of your working folder, named hdlsrc.

Before generating code, select Current Folder from the Desktop menu in the MATLAB window. This displays the Current Folder browser, which lets you access your working folder and the files that will be generated within it.

To generate code:

Click the Generate button.
As code generation proceeds, HDL Coder displays progress messages. The process should complete with the message
```
### HDL Code Generation Complete.
```
Observe that the names of generated files in the progress messages are hyperlinked. After code generation completes, you can click these hyperlinks to view the files in the MATLAB Editor.
HDL Coder compiles the model before generating code. Depending on model display options (such as port data types, etc.), the appearance of the model may change after code generation.
A folder icon for the hdlsrc folder is now visible in the Current Folder browser. To view generated code and script files, double-click the hdlsrc folder icon.
The files that were generated in the hdlsrc folder are:
- symmetric_fir.vhd: VHDL code. This file contains an entity definition and RTL architecture implementing the symmetric_fir filter.
- symmetric_fir_compile.do: Mentor Graphics ModelSim compilation script (vcom command) to compile the generated VHDL code.
- symmetric_fir_synplify.tcl: Synplify synthesis script.
- symmetric_fir_map.txt: Mapping file. This report file maps generated entities (or modules) to the subsystems that generated them (see Trace Code Using the Mapping File).
To view the generated VHDL code in the MATLAB Editor, double-click the symmetric_fir.vhd file icon in the Current Folder browser.
Before proceeding to the next section, close files you have opened in the editor. Then, click the Go Up One Level button in the Current Folder browser, to set the current folder back to your sl_hdlcoder_work folder.

Generating VHDL Test Bench Code

At this point, the Generate HDL for, Language, and Folder fields are set as they were in the previous section. Accordingly, you can now generate VHDL test bench code to drive the VHDL code generated previously for the sfir_fixed/symmetric_fir subsystem. The code will be written to the same target folder as before.

To generate a VHDL test bench:

Select the HDL Code Generation > Test Bench pane.
Select HDL test bench.
Click the Generate Test Bench button.
As test bench generation proceeds, HDL Coder displays progress messages. The process should complete with the message
```
### HDL TestBench Generation Complete.
```
The generated files in the hdlsrc folder are:
- symmetric_fir_tb.vhd: VHDL test bench code, with generated test and output data.
- symmetric_fir_tb_compile.do: Mentor Graphics ModelSim compilation script (vcom commands). This script compiles and loads the entity to be tested (symmetric_fir.vhd) and the test bench code (symmetric_fir_tb.vhd).
- symmetric_fir_tb_sim.do: Mentor Graphics ModelSim script to initialize the simulator, set up wave window signal displays, and run a simulation.

Verifying Generated Code

You can now take the generated code and test bench to an HDL simulator for simulated execution and verification of results. See Simulating and Verifying Generated HDL Code for an example of how to use generated test bench and script files with the Mentor Graphics ModelSim simulator.

Generating Verilog Model and Test Bench Code

The procedure for generating Verilog code is the same as for generating VHDL code (see Generating a VHDL Entity from a Subsystem and Generating VHDL Test Bench Code), except that you select Verilog from the Language field of the HDL Code Generation options.

Simulating and Verifying Generated HDL Code

Note: This section requires the use of the Mentor Graphics ModelSim simulator.

This section assumes that you have generated code from the sfir_fixed model as described in either of the following exercises:

In this section you compile and run a simulation of the previous generated model and test bench code. The scripts generated by HDL Coder let you do this with just a few simple commands. The procedure is the same, whether you generated code in the command line environment or in the GUI.

To run the simulation:

Start the Mentor Graphics ModelSim software.
Set the working folder to the folder in which you previously generated code.
```
ModelSim>cd C:/work/sl_hdlcoder_work/hdlsrc
```

Use the generated compilation script to compile and load the generated model and text bench code. The following listing shows the command and responses.

ModelSim>do symmetric_fir_tb_compile.do
# Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Compiling entity symmetric_fir
# -- Compiling architecture rtl of symmetric_fir
# Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Compiling package symmetric_fir_tb_pkg
# -- Compiling package body symmetric_fir_tb_pkg
# -- Loading package symmetric_fir_tb_pkg
# -- Loading package symmetric_fir_tb_pkg
# -- Compiling entity symmetric_fir_tb
# -- Compiling architecture rtl of symmetric_fir_tb
# -- Loading entity symmetric_fir

Use the generated simulation script to execute the simulation. The following listing shows the command and responses. The warning messages are benign.

ModelSim>do  symmetric_fir_tb_sim.do
# vsim work.symmetric_fir_tb 
# Loading C:\Applications\ModelTech_6_0\win32/../std.standard
# Loading C:\Applications\ModelTech_6_0\win32/../ieee.std_logic_1164(body)
# Loading C:\Applications\ModelTech_6_0\win32/../ieee.numeric_std(body)
# Loading work.symmetric_fir_tb_pkg(body)
# Loading work.symmetric_fir_tb(rtl)
# Loading work.symmetric_fir(rtl)
# ** Warning: NUMERIC_STD."<": metavalue detected, returning FALSE
#    Time: 0 ns  Iteration: 0  Instance: /symmetric_fir_tb
.
.
.
# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
#    Time: 0 ns  Iteration: 1  Instance: /symmetric_fir_tb
# ** Note: **************TEST COMPLETED **************
#    Time: 140 ns  Iteration: 1  Instance: /symmetric_fir_tb

The test bench termination message indicates that the simulation has run to completion without comparison errors.

# ** Note: **************TEST COMPLETED **************

The simulation script displays inputs and outputs in the model (including the reference signals y_out_ref and delayed_x_out_ref) in the Mentor Graphics ModelSim wave window. The following figure shows the signals displayed in the wave window.
Exit the Mentor Graphics ModelSim simulator when you finish viewing signals.
Close files you have opened in the MATLAB Editor. Then, click the Go Up One Level button in the Current Folder browser, to set the current folder back to your work folder.

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