Documentation

Global Settings Overview

The Global Settings pane enables you to specify detailed characteristics of the generated code, such as HDL element naming, and whether to map to a floating-point IP library.

Reset type

Specify whether to use asynchronous or synchronous reset logic when generating HDL code for registers.

Settings

Default: Asynchronous

Asynchronous

Use asynchronous reset logic.

Synchronous

Use synchronous reset logic.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

ResetType

Reset asserted level

Specify whether the asserted (active) level of reset input signal is active-high or active-low.

Settings

Default: Active-high

Active-high

Asserted (active) level of reset input signal is active-high (1).

Active-low

Asserted (active) level of reset input signal is active-low (0).

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

ResetAssertedLevel

Clock input port

Specify the name for the clock input port in generated HDL code.

Settings

Default: clk

Enter the clock signal name in generated HDL code as a character vector. If you specify a VHDL^® or Verilog^® reserved word, the code generator appends a reserved word postfix string to form a valid VHDL or Verilog identifier. For example, if you specify the reserved word signal, the resulting name string would be signal_rsvd.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

ClockInputPort

Clock enable input port

Specify the name for the clock enable input port in generated HDL code.

Settings

Default: clk_enable

Enter the clock enable input port name in generated HDL code as a character vector. If you specify a VHDL or Verilog reserved word, the code generator appends a reserved word postfix string to form a valid VHDL or Verilog identifier. For example, if you specify the reserved word signal, the resulting name string would be signal_rsvd.

Tip

The clock enable input signal is asserted active-high (1). Thus, the input value must be high for the generated entity's registers to be updated.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

ClockEnableInputPort

Reset input port

Enter the name for the reset input port in generated HDL code.

Settings

Default: reset

Enter a character vector for the reset input port name in generated HDL code. If you specify a VHDL or Verilog reserved word, the code generator appends a reserved word postfix string to form a valid VHDL or Verilog identifier. For example, if you specify the reserved word signal, the resulting name string would be signal_rsvd.

Tip

If the reset asserted level is set to active-high, the reset input signal is asserted active-high (1) and the input value must be high (1) for the entity's registers to be reset. If the reset asserted level is set to active-low, the reset input signal is asserted active-low (0) and the input value must be low (0) for the entity's registers to be reset.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

ResetInputPort

Clock inputs

Specify generation of single or multiple clock inputs.

Settings

Default: Single

Single

Generates a single clock input for the DUT. If the DUT is multirate, the input clock is the master clock rate, and a timing controller is synthesized to generate additional clocks as required.

Multiple

Generates a unique clock for each Simulink^® rate in the DUT. The number of timing controllers generated depends on the contents of the DUT.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

ClockInputs

Oversampling factor

Specify frequency of global oversampling clock as a multiple of the model's base rate.

Settings

Default: 1.

Oversampling factor specifies the oversampling factor of a global oversampling clock. The oversampling factor expresses the desired rate of the global oversampling clock as a multiple of your model's base rate. By default, HDL Coder™ does not generate a global oversampling clock.

If you want to generate a global oversampling clock:

• The Oversampling factor must be an integer greater than or equal to 1.

• In a multirate DUT, other rates in the DUT must divide evenly into the global oversampling rate.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

• Generate a Global Oversampling Clock

• Oversampling

Clock edge

Specify active clock edge.

Settings

Default: Rising.

Rising

The rising edge, or 0-to-1 transition, is the active clock edge.

Falling

The falling edge, or 1-to-0 transition, is the active clock edge.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

ClockEdge

Comment in header

Specify comment lines in header of generated HDL and test bench files.

Settings

Default: None

Text entered in this field generates a comment line in the header of generated model and test bench files. The code generator adds leading comment characters for the target language. When newlines or linefeeds are included, the code generator emits single-line comments for each newline.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

UserComment

Verilog file extension

Specify the file name extension for generated Verilog files.

Settings

Default: .v

This field specifies the file name extension for generated Verilog files.

Dependency

This option is enabled when the target language (specified by the Language option) is Verilog.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

VerilogFileExtension

VHDL file extension

Specify the file name extension for generated VHDL files.

Settings

Default: .vhd

This field specifies the file name extension for generated VHDL files.

Dependencies

This option is enabled when the target language (specified by the Language option) is VHDL.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

VHDLFileExtension

Entity conflict postfix

Specify the text as a character vector to resolve duplicate VHDL entity or Verilog module names in generated code.

Settings

Default: _block

The specified postfix resolves duplicate VHDL entity or Verilog module names. For example, in the default case, if HDL Coder detects two entities with the name MyFilt, the coder names the first entity MyFilt and the second instance MyFilt_entity.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

EntityConflictPostfix

Package postfix

Specify a text as a character vector to append to the model or subsystem name to form name of a package file.

Settings

Default: _pkg

HDL Coder applies this option only if a package file is required for the design.

Dependency

This option is enabled when:

The target language (specified by the Language option) is VHDL.

The target language (specified by the Language option) is Verilog, and the Multi-file test bench option is selected.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

PackagePostfix

Reserved word postfix

Specify a text as a character vector to append to value names, postfix values, or labels that are VHDL or Verilog reserved words.

Settings

Default: _rsvd

The reserved word postfix is applied to identifiers (for entities, signals, constants, or other model elements) that conflict with VHDL or Verilog reserved words. For example, if your generating model contains a signal named mod, HDL Coder adds the postfix _rsvd to form the name mod_rsvd.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

ReservedWordPostfix

Split entity and architecture

Specify whether generated VHDL entity and architecture code is written to a single VHDL file or to separate files.

Settings

Default: Off

On

VHDL entity and architecture definitions are written to separate files.

Off

VHDL entity and architecture code is written to a single VHDL file.

Tips

The names of the entity and architecture files derive from the base file name (as specified by the generating model or subsystem name). By default, postfix strings identifying the file as an entity (_entity) or architecture (_arch) are appended to the base file name. You can override the default and specify your own postfix as a character vector.

For example, instead of all generated code residing in MyFIR.vhd, you can specify that the code reside in MyFIR_entity.vhd and MyFIR_arch.vhd.

Dependencies

This option is enabled when the target language (specified by the Language option) is Verilog.

Selecting this option enables the following parameters:

• Split entity file postfix

• Split architecture file postfix

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

SplitEntityArch

Clocked process postfix

Specify a character vector to append to HDL clock process names.

Settings

Default: _process

HDL Coder uses process blocks for register operations. The label for each of these blocks is derived from a register name and the postfix _process. For example, the coder derives the label delay_pipeline_process from the register name delay_pipeline and the default postfix _process.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

ClockProcessPostfix

Complex real part postfix

Specify the character vector to append to real part of complex signal names.

Settings

Default: '_re'

Enter a text to be appended to the names generated for the real part of complex signals.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

ComplexRealPostfix

Complex imaginary part postfix

Specify character vector to append to imaginary part of complex signal names.

Settings

Default: '_im'

Enter a character vector to be appended to the names generated for the imaginary part of complex signals.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

ComplexImagPostfix

Split entity file postfix

Enter a character vector to be appended to the model name to form the name of a generated VHDL entity file.

Settings

Default: _entity

Dependencies

This parameter is enabled by Split entity and architecture.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

SplitEntityFilePostfix

Split arch file postfix

Enter a character vector to be appended to the model name to form the name of a generated VHDL architecture file.

Settings

Default: _arch

Dependency

This parameter is enabled by Split entity and architecture.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

SplitArchFilePostfix

VHDL architecture name

Specify the architecture name for your DUT in the generated HDL code.

Settings

Default: 'rtl'

Specify the VHDL architecture name for your DUT in the generated HDL code as a character vector.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

VHDLArchitectureName

Module name prefix

Specify a prefix for every module or entity name in the generated HDL code.

Settings

Default: ''

Specify a prefix for every module or entity name in the generated HDL code. HDL Coder also applies this prefix to generated script file names.

You can specify the module name prefix to avoid name collisions if you plan to instantiate the generated HDL code multiple times in a larger system.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

ModulePrefix

Enable prefix

Specify the base name as a character vector for internal clock enables and other flow control signals in generated code.

Settings

Default: 'enb'

Where only a single clock enable is generated, Enable prefix specifies the signal name for the internal clock enable signal.

In some cases, multiple clock enables are generated (for example, when a cascade block implementation for certain blocks is specified). In such cases, Enable prefix specifies a base signal name for the first clock enable that is generated. For other clock enable signals, numeric tags are appended to Enable prefix to form unique signal names. For example, the following code fragment illustrates two clock enables that were generated when Enable prefix was set to 'test_clk_enable':

COMPONENT mysys_tc
    PORT( clk                   :   IN    std_logic;
          reset                 :   IN    std_logic;
          clk_enable            :   IN    std_logic;
          test_clk_enable       :   OUT   std_logic;
          test_clk_enable_5_1_0 :   OUT   std_logic
          );
  END COMPONENT;

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

EnablePrefix

Pipeline postfix

Specify the postfix as a character vector to append to names of input or output pipeline registers generated for pipelined block implementations.

Settings

Default: '_pipe'

You can specify a generation of input and/or output pipeline registers for selected blocks. The Pipeline postfix option defines a character vector that HDL Coder appends to names of input or output pipeline registers.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

PipelinePostfix

Timing controller postfix

Specify the suffix appended to the DUT name to form the timing controller name.

Settings

Default: '_tc'

A timing controller file is generated if the design uses multiple rates, for example:

• When code is generated for a multirate model.

• When an area or speed optimization, or block architecture, introduces local multirate.

The timing controller name is based on the name of the DUT. For example, if the name of your DUT is my_test, by default, HDL Coder adds the postfix _tc to form the timing controller name, my_test_tc.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

TimingControllerPostfix

Generate VHDL code for model references into a single library

Specify whether VHDL code generated for model references is in a single library, or in separate libraries.

Settings

Default: Off

On

Generate VHDL code for model references into a single library.

Off

For each model reference, generate a separate VHDL library.

Dependencies

This option is enabled when the target language (specified by the Language option) is VHDL.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

UseSingleLibrary

VHDL library name

Specify the target library name for the generated VHDL code.

Settings

Default: 'work'

Target library name for generated VHDL code.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

• VHDLLibraryName

• HDLCompileInit

• UseSingleLibrary

Input data type

Specify the HDL data type for the model's input ports.

Settings

For VHDL, the options are:

Default: std_logic_vector

std_logic_vector

Specifies VHDL type STD_LOGIC_VECTOR.

signed/unsigned

Specifies VHDL type SIGNED or UNSIGNED.

For Verilog, the options are:

Default: wire

In generated Verilog code, the data type for all ports is 'wire'. Therefore, Input data type is disabled when the target language is Verilog.

Dependency

This option is enabled when the target language (specified by the Language option) is VHDL.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

InputType

Output data type

Specify the HDL data type for the model's output ports.

Settings

For VHDL, the options are:

Default: Same as input data type

Same as input data type

Specifies that output ports have the same type specified by Input data type.

std_logic_vector

Specifies VHDL type STD_LOGIC_VECTOR.

signed/unsigned

Specifies VHDL type SIGNED or UNSIGNED.

For Verilog, the options are:

Default: wire

In generated Verilog code, the data type for all ports is 'wire'. Therefore, Output data type is disabled when the target language is Verilog.

Dependency

This option is enabled when the target language (specified by the Language option) is VHDL.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

OutputType

Clock enable output port

Specify the name for the generated clock enable output.

Settings

Default: ce_out

A clock enable output is generated when the design requires one.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

ClockEnableOutputPort

Max oversampling

Specify the maximum oversampling ratio. The oversampling ratio is the sample rate after optimizations divided by the original model sample rate.

Use Max oversampling with Max computation latency to prevent or reduce overclocking by constraining resource sharing and streaming optimizations.

Settings

Default: 0

0

Do not set a limit on the maximum sample rate.

1

Do not allow oversampling.

N, where N is an integer greater than 1

Allow oversampling up to N times the original model sample rate.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

• MaxOversampling

• MaxComputationLatency

Max computation latency

Specify the maximum number of time steps for which your inputs are guaranteed to be stable.

Use Max computation latency with Max oversampling to prevent or reduce overclocking by constraining resource sharing and streaming optimizations.

Settings

Default: 1

1

DUT input data can change every cycle.

N, where N is an integer greater than 1

DUT input data can change every N cycles.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

• MaxComputationLatency

• MaxOversampling

Represent constant values by aggregates

Specify whether constants in VHDL code are represented by aggregates, including constants that are less than 32 bits.

Settings

Default: Off

On

HDL Coder represents constants as aggregates. The following VHDL constant declarations show a scalar less than 32 bits represented as an aggregate:

GainFactor_gainparam <= (14 => '1',  OTHERS => '0');

Off

The coder represents constants less than 32 bits as scalars and constants greater than or equal to 32 bits as aggregates. The following VHDL code was generated by default for a value less than 32 bits:

GainFactor_gainparam <= to_signed(16384, 16);

Dependencies

This option is enabled when the target language (specified by the Language option) is VHDL.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

UseAggregatesForConst

Use "rising_edge/falling_edge" style for registers

Specify whether generated code uses the VHDL rising_edge or falling_edge function to detect clock transitions.

Settings

Default: Off

On

Generated code uses the VHDL rising_edge or falling_edge function.

Off

Generated code uses the 'event syntax.

Dependencies

This option is enabled when the target language is VHDL.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

UseRisingEdge

Loop unrolling

Specify whether VHDL FOR and GENERATE loops are unrolled and omitted from generated VHDL code.

Settings

Default: Off

On

Unroll and omit FOR and GENERATE loops from the generated VHDL code. (In Verilog code, loops are always unrolled.)

Off

Include FOR and GENERATE loops in the generated VHDL code.

Tip

If you are using an electronic design automation (EDA) tool that does not support GENERATE loops, select this option to omit loops from your generated VHDL code.

Dependency

This option is enabled when the target language (specified by the Language option) is VHDL.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

LoopUnrolling

Use Verilog `timescale directives

Specify use of compiler `timescale directives in generated Verilog code.

Settings

Default: On

On

Use compiler `timescale directives in generated Verilog code.

Off

Suppress the use of compiler `timescale directives in generated Verilog code.

Tip

The `timescale directive provides a way of specifying different delay values for multiple modules in a Verilog file. This setting does not affect the generated test bench.

Dependency

This option is enabled when the target language (specified by the Language option) is Verilog.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

UseVerilogTimescale

Inline VHDL configuration

Specify whether generated VHDL code includes inline configurations.

Settings

Default: On

On

Include VHDL configurations in files that instantiate a component.

Off

Suppress the generation of configurations and require user-supplied external configurations. Use this setting if you are creating your own VHDL configuration files.

Tip

HDL configurations can be either inline with the rest of the VHDL code for an entity or external in separate VHDL source files. By default, HDL Coder includes configurations for a model within the generated VHDL code. If you are creating your own VHDL configuration files, suppress the generation of inline configurations.

Dependencies

This option is enabled when the target language (specified by the Language option) is VHDL.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

InlineConfigurations

Concatenate type safe zeros

Specify use of syntax for concatenated zeros in generated VHDL code.

Settings

Default: On

On

Use the type-safe syntax, '0' & '0', for concatenated zeros. Typically, this syntax is preferred.

Off

Use the syntax "000000..." for concatenated zeros. This syntax can be easier to read and more compact, but it can lead to ambiguous types.

Dependencies

This option is enabled when the target language (specified by the Language option) is VHDL.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

SafeZeroConcat

Emit time/date stamp in header

Specify whether or not to include time and date information in the generated HDL file header.

Settings

Default: On

On

Include time/date stamp in the generated HDL file header.

 -- ----------------------------------------------------
 -- 
 -- File Name: hdlsrc\symmetric_fir.vhd
 -- Created: 2011-02-14 07:21:36
 -- 

Off

Omit time/date stamp in the generated HDL file header.

 -- ----------------------------------------------------
 -- 
 -- File Name: hdlsrc\symmetric_fir.vhd
 -- 

By omitting the time/date stamp in the file header, you can more easily determine if two HDL files contain identical code. You can also avoid redundant revisions of the same file when checking in HDL files to a source code management (SCM) system.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

DateComment

Scalarize vector ports

Flatten vector ports into a structure of scalar ports in VHDL code

Settings

Default: Off

On

When generating code for a vector port, generate a structure of scalar ports.

Off

When generating code for a vector port, generate a type definition and port declaration for the vector port.

Dependencies

This option is enabled when the target language (specified by the Language option) is VHDL.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

ScalarizePorts

Minimize intermediate signals

Specify whether to optimize HDL code for debuggability or code coverage.

Settings

Default: Off

On

Optimize for code coverage by minimizing intermediate signals. For example, suppose that the generated code with this setting off is:

const3 <= to_signed(24, 7);
subtractor_sub_cast <= resize(const3, 8);
subtractor_sub_cast_1 <= resize(delayout, 8);
subtractor_sub_temp <= subtractor_sub_cast - subtractor_sub_cast_1;

With this setting on, HDL Coder optimizes the output to:

subtractor_sub_temp <= 24 - (resize(delayout, 8));

The coder removes the intermediate signals const3, subtractor_sub_cast, and subtractor_sub_cast_1.

Off

Optimize for debuggability by preserving intermediate signals.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

MinimizeIntermediateSignals

Include requirements in block comments

Enable or disable generation of requirements comments as comments in code or code generation reports

Settings

Default: On

On

If the model contains requirements comments, include them as comments in code or code generation reports. See Requirements Comments and Hyperlinks.

Off

Do not include requirements as comments in code or code generation reports.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

RequirementComments

Inline MATLAB Function block code

Inline HDL code for MATLAB Function blocks.

Settings

Default: Off

On

Inline HDL code for MATLAB Function blocks to avoid instantiation of code for custom blocks.

Off

Instantiate HDL code for MATLAB Function blocks and do not inline.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

InlineMATLABBlockCode

Generate parameterized HDL code from masked subsystem

Generate reusable HDL code for subsystems with the same tunable mask parameters, but with different values.

Settings

Default: Off

On

Generate one reusable HDL file for multiple masked subsystems with different values for the mask parameters. HDL Coder automatically detects subsystems with tunable mask parameters that are sharable.

Inside the subsystem, you can use the mask parameter only in the following blocks and parameters.

Block	Parameter	Limitation
Constant	Constant value on the Main tab of the dialog box	None
Gain	Gain on the Main tab of the dialog box	Parameter data type must be the same for all Gain blocks.

Off

Generate a separate HDL file for each masked subsystem.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

• Generate Reusable Code for Atomic Subsystems

• MaskParameterAsGeneric

Initialize all RAM blocks

Enable or suppress generation of initial signal value for RAM blocks.

Settings

Default: On

On

For RAM blocks, generate initial values of '0' for both the RAM signal and the output temporary signal.

Off

For RAM blocks, do not generate initial values for either the RAM signal or the output temporary signal.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

InitializeBlockRAM

RAM Architecture

Select RAM architecture with clock enable, or without clock enable, for all RAMs in DUT subsystem.

Settings

Default: RAM with clock enable

Select one of the following options from the menu:

• RAM with clock enable: Generate RAMs with clock enable.

• Generic RAM without clock enable: Generate RAMs without clock enable.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

RAMArchitecture

No-reset registers initialization

Specify whether you want to initialize registers without reset and the mode of initialization.

Settings

Default: Generate an external script

The options are:

Do not initialize

Select this option if you do not want HDL Coder to initialize the registers that do not have an external reset.

Generate an external reset

Select this option to generate an external script to initialize the no-reset registers for ModelSim^® simulation.

Generate initialization inside module

Select this option to generate the code for initializing the registers in the VHDL or Verilog code. In Verilog, HDL Coder initializes the registers by using an initial block in each module. In VHDL, HDL Coder initializes the registers as part of the signal declaration statements.

See Also

NoResetInitializationMode

HDL coding standard

Specify an HDL coding standard.

Settings

Default: None

None

Generate generic synthesizable HDL code.

Industry

Generate HDL code that follows the industry standard rules supported by the HDL Coder software. When this option is enabled, the coder generates a standard compliance report.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

HDLCodingStandard

Do not show passing rules in coding standard report

Specify whether to show rules without errors or warnings in the coding standard report.

Settings

Default: Off

On

Show only rules with errors or warnings.

Off

Show all rules.

Command-Line Information

To set this property:

1. Create an HDL coding standard customization object.

   cso = hdl.CodingStandard('Industry');

2. Set the ShowPassingRules property of the HDL coding standard customization object.

   For example, to omit passing rules from the report, enter:

   cso.ShowPassingRules.enable = false;

3. Set the HDLCodingStandardCustomizations property to the HDL coding standard customization object, specify the coding standard, and generate code.

   For example, if your DUT is sfir_fixed/symmetric_fir, enter:

   makehdl('sfir_fixed/symmetric_fir', 'HDLCodingStandard','Industry', ...
           'HDLCodingStandardCustomizations',cso);

See Also

HDL Coding Standard Customization

Check for duplicate names

Specify whether to check for duplicate names in the design (CGSL-1.A.A.5).

Settings

Default: On

On

Check for duplicate names.

Off

Do not check for duplicate names.

Command-Line Information

To set this property:

1. Create an HDL coding standard customization object.

   cso = hdl.CodingStandard('Industry');

2. Set the DetectDuplicateNamesCheck property of the HDL coding standard customization object.

   For example, to disable the check for duplicate names, enter:

   cso.DetectDuplicateNamesCheck.enable = false;

3. Set the HDLCodingStandardCustomizations property to the HDL coding standard customization object, specify the coding standard, and generate code.

   For example, if your DUT is sfir_fixed/symmetric_fir, enter:

   makehdl('sfir_fixed/symmetric_fir', 'HDLCodingStandard','Industry', ...
           'HDLCodingStandardCustomizations',cso);

See Also

HDL Coding Standard Customization

Check for HDL keywords in design names

Specify whether to check for HDL keywords in design names (CGSL-1.A.A.3).

Settings

Default: On

On

Check for HDL keywords in design names.

Off

Do not check for HDL keywords in design names.

Command-Line Information

To set this property:

1. Create an HDL coding standard customization object.

   cso = hdl.CodingStandard('Industry');

2. Set the HDLKeywords property of the HDL coding standard customization object.

   For example, to disable the check for HDL keywords in design names, enter:

   cso.HDLKeywords.enable = false;

3. Set the HDLCodingStandardCustomizations property to the HDL coding standard customization object, specify the coding standard, and generate code.

   For example, if your DUT is sfir_fixed/symmetric_fir, enter:

   makehdl('sfir_fixed/symmetric_fir', 'HDLCodingStandard','Industry', ...
           'HDLCodingStandardCustomizations',cso);

See Also

HDL Coding Standard Customization

Check for initial statements that set RAM initial values

Specify whether to check for initial statements that set RAM initial values (CGSL-2.C.D.1).

Settings

Default: On

On

Check for initial statements that set RAM initial values

Off

Do not check for initial statements that set RAM initial values.

Command-Line Information

To set this property:

1. Create an HDL coding standard customization object.

   cso = hdl.CodingStandard('Industry');

2. Set the InitialStatements property of the HDL coding standard customization object.

   For example, to disable the check for initial statements that set RAM initial values, enter:

   cso.InitialStatements.enable = false;

3. Set the HDLCodingStandardCustomizations property to the HDL coding standard customization object, specify the coding standard, and generate code.

   For example, if your DUT is sfir_fixed/symmetric_fir, enter:

   makehdl('sfir_fixed/symmetric_fir', 'HDLCodingStandard','Industry', ...
           'HDLCodingStandardCustomizations',cso);

See Also

HDL Coding Standard Customization

Check module, instance, and entity name length

Specify whether to check module, instance, and entity name length (CGSL-1.A.C.3).

Settings

Default: On

On

Check module, instance, and entity name length.

Minimum

Minimum name length, specified as a positive integer. The default is 2.

Maximum

Maximum name length, specified as a positive integer. The default is 32.

Off

Do not check module, instance, and entity name length.

Command-Line Information

To set this property:

1. Create an HDL coding standard customization object.

   cso = hdl.CodingStandard('Industry');

2. Set the ModuleInstanceEntityNameLength property of the HDL coding standard customization object.

   For example, to enable the check for module, instance, and entity name length, with 5 as the minimum length and 30 as the maximum length, enter:

   cso.ModuleInstanceEntityNameLength.enable = true;
   cso.ModuleInstanceEntityNameLength.length = [5 30];

3. Set the HDLCodingStandardCustomizations property to the HDL coding standard customization object, specify the coding standard, and generate code.

   For example, if your DUT is sfir_fixed/symmetric_fir, enter:

   makehdl('sfir_fixed/symmetric_fir', 'HDLCodingStandard','Industry', ...
           'HDLCodingStandardCustomizations',cso);

See Also

HDL Coding Standard Customization

Check signal, port, and parameter name length

Specify whether to check signal, port, and parameter name length (CGSL-1.A.B.1).

Settings

Default: On

On

Check signal, port, and parameter name length.

Minimum

Minimum name length, specified as a positive integer. The default is 2.

Maximum

Maximum name length, specified as a positive integer. The default is 40.

Off

Do not check signal, port, and parameter name length.

Command-Line Information

To set this property:

1. Create an HDL coding standard customization object.

   cso = hdl.CodingStandard('Industry');

2. Set the SignalPortParamNameLength property of the HDL coding standard customization object.

   For example, to enable the check for signal, port, and parameter name length, with 5 as the minimum length and 30 as the maximum length, enter:

   cso.SignalPortParamNameLength.enable = true;
   cso.SignalPortParamNameLength.length = [5 30];

3. Set the HDLCodingStandardCustomizations property to the HDL coding standard customization object, specify the coding standard, and generate code.

   For example, if your DUT is sfir_fixed/symmetric_fir, enter:

   makehdl('sfir_fixed/symmetric_fir', 'HDLCodingStandard','Industry', ...
           'HDLCodingStandardCustomizations',cso);

See Also

HDL Coding Standard Customization

Minimize use of clock enable signals

Specify whether to check for clock enable signals in the generated code (CGSL-2.C.C.4).

Settings

Default: Off

On

Minimize clock enables during code generation, then check for clock enable signals in the generated code.

Off

Do not check for clock enable signals in the generated code.

Command-Line Information

To set this property:

1. Create an HDL coding standard customization object.

   cso = hdlcoder.CodingStandard('Industry');

2. Set the MinimizeClockEnableCheck property of the HDL coding standard customization object.

   For example, to minimize clock enables and check for clock enable signals in the generated code, enter:

   cso.MinimizeClockEnableCheck.enable = true;

3. Set the HDLCodingStandardCustomizations property to the HDL coding standard customization object, specify the coding standard, and generate code.

   For example, if your DUT is sfir_fixed/symmetric_fir, enter:

   makehdl('sfir_fixed/symmetric_fir', 'HDLCodingStandard','Industry', ...
           'HDLCodingStandardCustomizations',cso);

See Also

• HDL Coding Standard Customization

• Minimize Clock Enables

Detect usage of reset signals

Specify whether to check for reset signals in the generated code (CGSL-2.C.C.5).

Settings

Default: Off

On

Minimize reset signals in the generated code, then check for reset signals after code generation.

Off

Do not check for reset signals in the generated code.

Command-Line Information

To set this property:

1. Create an HDL coding standard customization object.

   cso = hdlcoder.CodingStandard('Industry');

2. Set the RemoveResetCheck property of the HDL coding standard customization object.

   For example, to check for reset signals, enter:

   cso.RemoveResetCheck.enable = true;

3. Set the HDLCodingStandardCustomizations property to the HDL coding standard customization object, specify the coding standard, and generate code.

   For example, if your DUT is sfir_fixed/symmetric_fir, enter:

   makehdl('sfir_fixed/symmetric_fir', 'HDLCodingStandard','Industry', ...
           'HDLCodingStandardCustomizations',cso);

See Also

HDL Coding Standard Customization

Detect usage of asynchronous reset signals

Specify whether to check for asynchronous reset signals in the generated code (CGSL-2.C.C.6).

Settings

Default: Off

On

Check for asynchronous reset signals in the generated code.

Off

Do not check for asynchronous reset signals in the generated code.

Command-Line Information

To set this property:

1. Create an HDL coding standard customization object.

   cso = hdlcoder.CodingStandard('Industry');

2. Set the AsynchronousResetCheck property of the HDL coding standard customization object.

   For example, to minimize use of variables, enter:

   cso.AsynchronousResetCheck.enable = true;

3. Set the HDLCodingStandardCustomizations property to the HDL coding standard customization object, specify the coding standard, and generate code.

   For example, if your DUT is sfir_fixed/symmetric_fir, enter:

   makehdl('sfir_fixed/symmetric_fir', 'HDLCodingStandard','Industry', ...
           'HDLCodingStandardCustomizations',cso);

See Also

HDL Coding Standard Customization

Check for conditional statements in processes

Specify whether to check for length of conditional statements that are described separately within a process (CGSL-2.F.B.1).

Settings

Default: On

On

Check for length of conditional statements in a process. The default length is 1.

Off

Do not check for length of conditional statements in a process.

Command-Line Information

To set this property:

1. Create an HDL coding standard customization object.

   cso = hdlcoder.CodingStandard('Industry');

2. Set the ConditionalRegionCheck property of the HDL coding standard customization object.

   For example, to check for four conditional statements in a process, enter:

   cso.ConditionalRegionCheck.enable = true;
   cso.ConditionalRegionCheck.length = 4;

3. Set the HDLCodingStandardCustomizations property to the HDL coding standard customization object, specify the coding standard, and generate code.

   For example, if your DUT is sfir_fixed/symmetric_fir, enter:

   makehdl('sfir_fixed/symmetric_fir', 'HDLCodingStandard','Industry', ...
           'HDLCodingStandardCustomizations',cso);

See Also

HDL Coding Standard Customization

Minimize use of variables

Specify whether to minimize use of variables (CGSL-2.G).

Settings

Default: Off

On

Minimize use of variables.

Off

Do not minimize use of variables.

Command-Line Information

To set this property:

1. Create an HDL coding standard customization object.

   cso = hdlcoder.CodingStandard('Industry');

2. Set the MinimizeVariableUsage property of the HDL coding standard customization object.

   For example, to minimize use of variables, enter:

   cso.MinimizeVariableUsage.enable = true;

3. Set the HDLCodingStandardCustomizations property to the HDL coding standard customization object, specify the coding standard, and generate code.

   For example, if your DUT is sfir_fixed/symmetric_fir, enter:

   makehdl('sfir_fixed/symmetric_fir', 'HDLCodingStandard','Industry', ...
           'HDLCodingStandardCustomizations',cso);

See Also

HDL Coding Standard Customization

Check if-else statement chain length

Specify whether to check if-else statement chain length (CGSL-2.G.C.1c).

Settings

Default: On

On

Check if-else statement chain length.

Length

Maximum if-else statement chain length, specified as a positive integer. The default is 7.

Off

Do not check if-else statement chain length.

Command-Line Information

To set this property:

1. Create an HDL coding standard customization object.

   cso = hdl.CodingStandard('Industry');

2. Set the IfElseChain property of the HDL coding standard customization object.

   For example, to check for if-else statement chains with length greater than 5, enter:

   cso.IfElseChain.enable = true;
   cso.IfElseChain.length = 5;

3. Set the HDLCodingStandardCustomizations property to the HDL coding standard customization object, specify the coding standard, and generate code.

   For example, if your DUT is sfir_fixed/symmetric_fir, enter:

   makehdl('sfir_fixed/symmetric_fir', 'HDLCodingStandard','Industry', ...
           'HDLCodingStandardCustomizations',cso);

See Also

HDL Coding Standard Customization

Check if-else statement nesting depth

Specify whether to check if-else statement nesting depth (CGSL-2.G.C.1a).

Settings

Default: On

On

Check if-else statement nesting depth.

Depth

Maximum if-else statement nesting depth, specified as a positive integer. The default is 3.

Off

Do not check if-else statement nesting depth.

Command-Line Information

To set this property:

1. Create an HDL coding standard customization object.

   cso = hdl.CodingStandard('Industry');

2. Set the IfElseNesting property of the HDL coding standard customization object.

   For example, to enable the check for if-else statement nesting depth with a maximum depth of 5, enter:

   cso.IfElseNesting.enable = true;
   cso.IfElseNesting.depth = 5;

3. Set the HDLCodingStandardCustomizations property to the HDL coding standard customization object, specify the coding standard, and generate code.

   For example, if your DUT is sfir_fixed/symmetric_fir, enter:

   makehdl('sfir_fixed/symmetric_fir', 'HDLCodingStandard','Industry', ...
           'HDLCodingStandardCustomizations',cso);

See Also

HDL Coding Standard Customization

Check multiplier width

Specify whether to check multiplier bit width (CGSL-2.J.F.5).

Settings

Default: On

On

Check multiplier width.

Maximum

Maximum multiplier bit width, specified as a positive integer. The default is 16.

Off

Do not check multiplier width.

Command-Line Information

To set this property:

1. Create an HDL coding standard customization object.

   cso = hdl.CodingStandard('Industry');

2. Set the MultiplierBitWidth property of the HDL coding standard customization object.

   For example, to enable the check for multiplier width with a maximum bit width of 32, enter:

   cso.MultiplierBitWidth.enable = true;
   cso.MultiplierBitWidth.width = 32;

3. Set the HDLCodingStandardCustomizations property to the HDL coding standard customization object, specify the coding standard, and generate code.

   For example, if your DUT is sfir_fixed/symmetric_fir, enter:

   makehdl('sfir_fixed/symmetric_fir', 'HDLCodingStandard','Industry', ...
           'HDLCodingStandardCustomizations',cso);

See Also

HDL Coding Standard Customization

Check for non-integer constants

Specify whether to check for non-integer constants (CGSL-3.B.D.1).

Settings

Default: On

On

Check for non-integer constants.

Off

Do not check for non-integer constants.

Command-Line Information

To set this property:

1. Create an HDL coding standard customization object.

   cso = hdl.CodingStandard('Industry');

2. Set the NonIntegerTypes property of the HDL coding standard customization object.

   For example, to disable the check for non-integer constants, enter:

   cso.NonIntegerTypes.enable = false;

3. Set the HDLCodingStandardCustomizations property to the HDL coding standard customization object, specify the coding standard, and generate code.

   For example, if your DUT is sfir_fixed/symmetric_fir, enter:

   makehdl('sfir_fixed/symmetric_fir', 'HDLCodingStandard','Industry', ...
           'HDLCodingStandardCustomizations',cso);

See Also

HDL Coding Standard Customization

Check line length

Specify whether to check line lengths in the generated HDL code (CGSL-3.A.D.5).

Settings

Default: On

On

Check line length.

Maximum

Maximum number of characters in a line, specified as a positive integer. The default is 110.

Off

Do not check line length.

Command-Line Information

To set this property:

1. Create an HDL coding standard customization object.

   cso = hdl.CodingStandard('Industry');

2. Set the LineLength property of the HDL coding standard customization object.

   For example, to enable the check line length with a maximum character length of 80, enter:

   cso.HDLKeywordsLineLength.enable = true;
   cso.HDLKeywordsLineLength.length = 80;

3. Set the HDLCodingStandardCustomizations property to the HDL coding standard customization object, specify the coding standard, and generate code.

   For example, if your DUT is sfir_fixed/symmetric_fir, enter:

   makehdl('sfir_fixed/symmetric_fir', 'HDLCodingStandard','Industry', ...
           'HDLCodingStandardCustomizations',cso);

See Also

HDL Coding Standard Customization

Highlight feedback loops inhibiting delay balancing and optimizations

Specify whether to generate a script to highlight feedback loops that are inhibiting delay balancing and optimizations.

Settings

Default: Off

On

Generate a MATLAB^® script that highlights feedback loops in the original model and generated model.

Off

Do not generate a script to highlight feedback loops.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

• HighlightFeedbackLoops

• HighlightFeedbackLoopsFile

• Find Feedback Loops

Highlight blocks inhibiting clock-rate pipelining

Specify whether to generate a script to highlight blocks that are inhibiting clock-rate pipelining.

Settings

Default: Off

On

Generate a MATLAB script that highlights blocks in the original model and generated model that are inhibiting clock-rate pipelining.

Off

Do not generate a script to highlight blocks that are inhibiting clock-rate pipelining.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

• HighlightClockRatePipeliningDiagnostic

• HighlightClockRatePipeliningFile

Highlight blocks inhibiting distributed pipelining

Specify whether to generate a script to highlight blocks that are inhibiting distributed pipelining.

Settings

Default: Off

On

Generate a MATLAB script that highlights blocks that are inhibiting distributed pipelining in the original model and generated model.

Off

Do not generate a script to highlight blocks that are inhibiting distributed pipelining.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

• DistributedPipeliningBarriers

• DistributedPipeliningBarriersFile

Check for name conflicts in black box interfaces

Specify whether to check for duplicate module or entity names in generated HDL code and black box interface HDL code.

Settings

Default: Warning

None

Do not check for black box subsystems that have the same HDL module name as a generated HDL module name.

Warning

Check for black box subsystems that have the same HDL module name as a generated HDL module name. Display a warning if matching names are found.

Error

Check for black box subsystems that have the same HDL module name as a generated HDL module name. Display an error if matching names are found.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

• DetectBlackBoxNameCollision

Library

Specify the floating-point target library

Settings

Default: NONE

The options are:

NONE

Select this option if you do not want the design to map to floating-point target libraries.

ALTERA MEGAFUNCTION (ALTERA FP FUNCTIONS)

Specify Altera^® megafunction (ALTERA FP FUNCTIONS) as the floating-point target library. You can provide the IP Target frequency.

ALTERA MEGAFUNCTION (ALTFP)

Specify Altera megafunction (ALTFP) as the floating-point target library. You can provide the objective and latency strategy for the IP.

XILINX LOGICORE

Specify Xilinx^® LogiCORE as the floating-point target library. You can provide the objective and latency strategy for the IP.

NATIVE FLOATING POINT

Specify native floating-point as the library. You can specify the latency strategy and whether to handle denormals in your design.

See Also

• NativeFloatingPoint

Initialize IP Pipelines To Zero

Inserts additional logic during HDL code generation to initialize the values of pipeline registers in the Altera floating-point target IP to zero. If you do not select the check box, HDL Coder reports a warning during HDL code generation.

Settings

Default: On

On

Inserts additional logic to initialize pipeline registers in the floating-point target IP to zero.

Off

Does not add additional logic to initialize pipeline registers in the floating-point target IP to zero.

Latency Strategy

Specify whether you want the design to map to minimum or maximum latency with Xilinx LogiCORE or ALTFP Altera megafunction IPs.

Settings

Default: MIN

The options are:

MIN

Maps to minimum latency for the specified floating-point target IP.

MAX

Maps to maximum latency for the specified floating-point target IP.

See also

• Generate HDL Code for FPGA Floating-Point Target Libraries

• Customize Floating-Point IP Configuration

Objective

Specify whether you want to optimize the design for speed or area when mapping to floating-point target libraries.

Settings

Default: SPEED

The options are:

NONE

Select this option if you do not want to optimize the design for speed or area.

SPEED

Select this option to optimize the design for speed.

AREA

Select this option to optimize the design for area.

See also

• Generate HDL Code for FPGA Floating-Point Target Libraries

• Customize Floating-Point IP Configuration

IP Settings

The IP Settings section has an IP configuration table with the IP names and data types and additional options to specify a custom latency and any extra arguments.

The options in the IP configuration table depend on the library that you specify.

• If you specify the ALTERA MEGAFUNCTION (ALTERA FP FUNCTIONS) library, HDL Coder infers the latency value from the Target Frequency (MHz) value.

• If you specify the ALTERA MEGAFUNCTION (ALTFP) or XILINX LOGICORE libraries, HDL Coder infers the IP latency from the Latency Strategy setting. The IP configuration table has two additional columns, MinLatency and MaxLatency, that contain the minimum and maximum latency values for each IP in the table.

The IP configuration table has these sections:

• Name: Contains a list of IP names that HDL Coder map the Simulink blocks to, such as ABS, ADDSUB, and CONVERT.

• DataType: Contains a list of IP data types for each IP in the table. These are mostly SINGLE and DOUBLE data types. The CONVERT IP blocks can have DOUBLE_TO_NUMERICTYPE, NUMERICTYPE_TO_DOUBLE data types, and so on.

• Latency: The default latency value of –1 means that the IP inherits the latency value from the target frequency or the latency strategy setting depending on the library that you choose. To customize the latency of the IP that your Simulink blocks map to, enter your own custom value for the latency.

• ExtraArgs: Specify any additional settings that is specific to the IP.

For example, if you have an Add block with Single data types in your Simulink model, HDL Coder maps the block to the ADDSUB IP. If you want to specify a custom latency value, say 8, for the IP, enter the value in the Latency column for the IP.

cmultusage is a parameter that you can specify with the Xilinx LogiCORE^® libraries.

See also

• Generate HDL Code for FPGA Floating-Point Target Libraries

• Customize Floating-Point IP Configuration

Latency Strategy

Specify whether you want the design to map to minimum or maximum latency with native floating-point libraries.

Settings

Default: MAX

The options are:

MIN

Maps to minimum latency for the native floating-point libraries.

MAX

Maps to maximum latency for the native floating-point libraries.

ZERO

Does not use any latency for the native floating-point libraries.

See also

• Generate Target-Independent HDL Code with Native Floating-Point

• Latency Customization with Native Floating-Point

Handle Denormals

Specify whether you want to handle denormal numbers in your design. Denormal numbers are nonzero numbers that are smaller than the smallest normal number.

Settings

Default: Off

On

Inserts additional logic to handle the denormal numbers in your design.

Off

Does not add additional logic to handle the denormal numbers in your design. If the input is a denormal value, HDL Coder treats the value as zero before performing any computations.

See also

• Generate Target-Independent HDL Code with Native Floating-Point

• Numerical Considerations with Native Floating-Point

Mantissa Multiplier Strategy

Specify how you want HDL Coder to implement the mantissa multiplication operation when you have Product blocks in your design.

Settings

Default: Full Multiplier

The options are:

Full Multiplier

Specify this option to use only multipliers for implementing the mantissa multiplication. The multipliers can utilize DSP units on the target device.

Part Multiplier Part AddShift

Specify this option to split the implementation into two parts. One part is implemented with multipliers. The other part is implemented with a combination of adders and shifters. The multipliers can utilize the DSP units on the target device. The combination of adders and shifters does not utilize the DSP.

No Multiplier Full AddShift

Select this option to use a combination of adders and multipliers to implement the mantissa multiplication. This option does not utilize DSP units on the target device. You can also use this option if your target device does not contain DSP units.

See also

• Generate Target-Independent HDL Code with Native Floating-Point

• Numerical Considerations with Native Floating-Point

• Latency Customization with Native Floating-Point