When generating code with native floating-point, you can customize the latency in three ways.
Latency Strategy setting: Specify whether to map your Simulink® model to maximum, minimum, or zero latency of the floating-point operator.
Oversampling factor: The design operates at a faster clock-rate and absorbs the clock-rate pipelines with the latency of the floating-point operator.
Delay blocks in the model: If your Simulink model has a latency, HDL Coder™ can absorb some or all of the latency with the native floating-point implementation.
When generating code by using HDL Coder native floating-point, you can specify whether to use zero, minimum, or maximum latency for the floating-point operators. If you specify maximum or minimum latency, you can get the latency information of the floating-point operator from the generated model.
To specify this setting from the Configuration Parameters dialog box:
In the HDL Code Generation > Global Settings > Floating Point
Target tab, for Library,
select Native Floating Point
.
For Latency Strategy, specify MAX
, MIN
,
or ZERO
.
To specify this setting from the command-line:
Create a hdlcoder.FloatingPointTargetConfig
object:
Use the hdlcoder.createFloatingPointTargetConfig
function
to create a native floating-point configuration object.
nfpconfig = hdlcoder.createFloatingPointTargetConfig('NATIVEFLOATINGPOINT'); hdlset_param('sfir_single', 'FloatingPointTargetConfiguration', nfpconfig);
Specify the latency strategy: If you have denormal numbers in your design, you can configure the native floating-point library to handle denormals.
nfpconfig.LibrarySettings.LatencyStrategy = 'MAX'
When you design the blocks in your Simulink model at the data rate, specify an Oversampling factor greater than one. The blocks now operate at a faster clock rate instead of the data rate. The oversampling factor inserts pipeline registers at the clock rate, which improves clock frequency and reduces area usage. To learn more about clock-rate pipelining, see Clock-Rate Pipelining.
This Add block has inputs of Single
data
type, and has a latency of 1. The model is operating at a sample time
of 1. The Oversampling factor of the model is
set to 40
.
After HDL code generation, the generated model shows the NFP add block. The NFP add block corresponds to HDL Coder implementation of the floating-point add operation.
The NFP add block is operating at a clock rate that is 40 times faster than the Add block in your model. The block absorbed the Delay block in your Simulink model, which now operates at the clock rate. This implementation saves area by absorbing the additional latency, and improves timing by operating at the faster clock rate.
If your Simulink model has a latency, HDL Coder absorbs some or all of the latency with the native floating-point operator implementation.
If you have a Delay block in your design with Delay length less than or equal to the latency of the floating-point operator, HDL Coder absorbs the latency inside the operator. This latency absorption avoids some of the additional latency in your model.
Consider this Simulink model that compares the results of a square root and an exponential operation. The latency strategy setting uses the maximum latency.
When generating HDL code, the generated model shows how HDL Coder implemented the floating-point operators.
The NFP Sqrt block has a maximum latency
of 28
. This latency is equal to the Delay
length of the Delay block at the output
of your Simulink model. HDL Coder absorbs the Delay inside
the NFP Sqrt block.
The NFP math block has a maximum latency
of 23
. This latency is less than the Delay
length of the Delay block at the output
of your Simulink model. HDL Coder absorbs a Delay
length equal to the latency of the floating-point operator.
A Delay block with the excess Delay length appears
outside the operator.
To learn more about the supported operators and their maximum and minimum latency values, see Operators and Simulink Blocks Supported for Native Floating-Point.