Documentation

With HDL Coder™ native floating-point support, you can generate target-independent HDL code. You can synthesize your floating-point design on any generic FPGA or ASIC.

Eliminating the floating-point to fixed-point conversion step reduces the loss of data precision, and enables you to model a wider dynamic range.

How HDL Coder Generates Target-Independent HDL Code

This figure shows how HDL Coder generates code with the native floating-point technology.

The Unpack and Pack blocks convert the single-precision types to the sign, exponent, and mantissa. In the figure, S, E, and M represent the sign, exponent, and mantissa respectively. This interpretation is based on the IEEE-754 standard of floating-point arithmetic.

The Floating-Point Algorithm Implementation block performs computations on the S, E, and M. With this conversion, the generated HDL code is target-independent. You can deploy the design on any generic FPGA or an ASIC.

Modeling Floating-Point Designs

Sometimes, you want to model your design with floating-point types to:

• Implement algorithms that have a large or unknown dynamic range that can fall outside the range of representable fixed-point types.

• Implement complex math and trigonometric operations that are difficult to design in fixed point.

• Obtain a higher precision and better accuracy.

Floating-point designs can potentially occupy more area on the target hardware. To design for these trade-offs, in your Simulink^® model, you can use floating-point and fixed-point data types. By using Data Type Conversion blocks, you can perform conversions between the floating-point and fixed-point types. This figure shows a section of a Simulink model that uses Single and fixed-point types.

Generate Code

You can generate code in the Configuration Parameters dialog box or at the command line.

To specify the native floating-point settings and generate HDL code in the Configuration Parameters dialog box:

1. In the HDL Code Generation > Global Settings > Floating Point Target tab, for Library, specify Native Floating Point.

   

2. Specify the Latency Strategy to map your design to maximum or minimum latency or no latency.

3. If you have denormal numbers in your design, select Handle Denormals. Denormal numbers are numbers that have an exponent field equal to zero and a nonzero mantissa field. See Handle Denormals.

4. If your design has Product blocks, to specify how you want HDL Coder to implement the multiplication operation, use the Mantissa Multiplier Strategy. See Mantissa Multiplier Strategy.

5. To share floating-point resources, on the HDL Code Generation > Target and Optimizations > Resource Sharing tab, make sure that you select Floating-point IPs. The number of blocks that get shared depends on the SharingFactor that you specify for the subsystem.

6. Click Apply. You can now generate HDL code from your Simulink model. (see HDL Code Generation from a Simulink Model)

To generate HDL code at the command line, use the:

• NativeFloatingPoint property: To generate code with the default settings for the native floating-point library, use the makehdl function. For example, to enable NativeFloatingPoint for an sfir_single/symmetric_fir subsystem and generate HDL code, enter:

  makehdl ('sfir_single/symmetric_sfir','NativeFloatingPoint','on')

• hdlcoder.createFloatingPointTargetConfig function: You can use this function to create an hdlcoder.FloatingPointTargetConfig object for the native floating-point library.

  nfpconfig = hdlcoder.createFloatingPointTargetConfig('NATIVEFLOATINGPOINT');
  hdlset_param('sfir_single', 'FloatingPointTargetConfiguration', nfpconfig);

  Optionally, you can specify the latency strategy and whether you want HDL Coder to handle denormal numbers in your design:

  nfpconfig.LibrarySettings.HandleDenormals = 'on';
  nfpconfig.LibrarySettings.LatencyStrategy = 'MAX';

To learn how you can verify the generated code, see Verify the Generated Code from Native Floating-Point.

View Code Generation Report

To view the code generation reports of floating-point library mapping, before you begin code generation, enable generation of the Resource Utilization Report and Optimization Report. To enable the reports, in the Configuration Parameters dialog box, on the HDL Code Generation pane, enable Generate resource utilization report and Generate optimization report. See also Create and Use Code Generation Reports.

Native Floating-Point Resource Report

To see the list of native floating-point operators that HDL Coder supports and the floating-point operators to which your Simulink blocks mapped to, in the Code Generation Report, select Native Floating-Point Resource Report.

A detailed report shows the various resources that the floating-point adder and multiplier uses on the target device that you specify.

To learn more about the Resource Utilization report, see Resource Utilization Report.

Target Code Generation Report

To see the native floating-point settings that you applied to the model and whether HDL Coder successfully generated HDL code, in the Code Generation Report, select Target Code Generation.

To learn more about the Optimization report, see Optimization Report.

Analyze Results

If you select maximum or minimum latency for the latency strategy, you can get the latency information of the floating-point operator from the generated model.

This Simulink model has a Single input and has Latency Strategy set to MIN.

After HDL code generation, the generated model shows the native floating-point operators corresponding to the blocks in your Simulink model.

To get the latency information of the floating-point operator, double-click that NFP block. For example, if you double-click the NFP sqrt block, you can get the latency of the floating-point reciprocal square-root implementation. Here, the latency is 17.

To learn more about the generated model, see Generated Model and Validation Model.

You can customize the latency of the floating-point operators that your design uses. See Latency Customization with Native Floating-Point.