Documentation

Target and Optimizations Overview

The Target and Optimizations pane enables you to specify the target hardware and apply certain optimizations to the generated HDL code.

Tool and Device

Select a synthesis tool, then select the Family, Device, Package, and Speed for your synthesis target.

Settings

Default: No synthesis tool specified

The options are:

No synthesis tool specified

Select this option if you do not want to perform logic synthesis. You can generate HDL code from your design.

Xilinx Vivado

Specify Xilinx^® Vivado as the synthesis tool.

Xilinx ISE

Specify Xilinx ISE as the synthesis tool.

Altera Quartus II

Specify Altera^® Quartus II as the synthesis tool.

If your synthesis tool is not one of the Synthesis tool options, see Synthesis Tool Path Setup.

Target Frequency

Specify the target frequency in MHz for multiple features and workflows.

Settings

Default: 0

This setting is the target frequency in MHz for multiple features and workflows that HDL Coder™ supports. The supported features are:

• FPGA floating-point target library mapping: Specify the target frequency that you want the IP to achieve when you use ALTERA MEGAFUNCTION (ALTERA FP FUNCTIONS). If you do not specify the target frequency, HDL Coder sets the target frequency to a default value of 200 MHz.

• Adaptive pipelining: If your design uses multipliers, specify the synthesis tool and the target frequency. Based on these settings, HDL Coder estimates the number of pipelines that can be inserted to improve area and timing on the target platform. If you do not specify the target frequency, HDL Coder uses a target frequency of 0 MHz and cannot insert any pipelines.

You can also set the target frequency by using the Target Frequency (MHz) setting in the Set Target Frequency task in the HDL Workflow Advisor.

Specify the target frequency for these workflows-

• Generic ASIC/FPGA: To specify the target frequency that you want your design to achieve. HDL Coder generates a timing constraint file for that clock frequency. It adds the constraint to the FPGA synthesis tool project that you create in the Create Project task. If the target frequency is not achievable, the synthesis tool generates an error.

• IP Core Generation: To specify the target frequency for HDL Coder to modify the clock module setting in the reference design to produce the clock signal with that frequency. Enter a target frequency value that is within the Frequency Range (MHz). If you do not specify the target frequency, HDL Coder uses the Default (MHz) target frequency.

• Simulink Real-Time FPGA I/O: For Speedgoat boards that are supported with Xilinx ISE, specify the target frequency to generate the clock module to produce the clock signal with that frequency.

  The Speedgoat boards that are supported with Xilinx Vivado use the IP Core Generation workflow infrastructure. Specify the target frequency for HDL Coder to modify the clock module setting in the reference design to produce the clock signal with that frequency. Enter a target frequency value that is within the Frequency Range (MHz). If you do not specify the target frequency, HDL Coder uses the Default (MHz) target frequency.

• FPGA Turnkey: To generate the clock module to produce the clock signal with that frequency automatically.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

• TargetFrequency

• Set Target Frequency

• Customize Floating-Point IP Configuration

Balance delays

Enable delay balancing.

Settings

Default: On

On

If HDL Coder detects introduction of new delays along one path, matching delays are inserted on the other paths. When delay balancing is enabled, the generated model is functionally equivalent to the original model.

Off

The latency along signal paths might not be balanced, and the generated model might not be functionally equivalent to the original model.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

Delay Balancing

Map pipeline delays to RAM

Map pipeline registers in the generated HDL code to RAM.

Settings

Default: Off

On

Map pipeline registers in the generated HDL code to RAM.

Off

Do not map pipeline registers in the generated HDL code to RAM.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

MapPipelineDelaysToRAM

Optimize timing controller

Optimize timing controller entity for speed and code size by implementing separate counters per rate.

Settings

Default: On

On

HDL Coder generates multiple counters (one counter for each rate in the model) in the timing controller code. The benefit of this optimization is that it generates faster logic, and the size of the generated code is usually much smaller.

Off

The coder generates a timing controller that uses one counter to generate all rates in the model.

Tip

A timing controller code file is generated if required by the design, for example:

• When code is generated for a multirate model

• When a cascade block implementation for certain blocks is specified

This file contains a module defining timing signals (clock, reset, external clock enable inputs and clock enable output) in a separate entity or module. In a multirate model, the timing controller entity generates the required rates from a single master clock using one or more counters and multiple clock enables.

The timing controller name derives from the name of the subsystem that is selected for code generation (the DUT), and the current value of the property TimingControllerPostfix. For example, if the name of your DUT is my_test, in the default case the coder adds the TimingControllerPostfix _tc to form the timing controller name my_test_tc.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

OptimizeTimingController

Minimize clock enables

Omit generation of clock enable logic for single-rate designs.

Settings

Default: Off

On

For single-rate models, omit generation of clock enable logic wherever possible. The following VHDL^® code example does not define or examine a clock enable signal. When the clock signal (clk) goes high, the current signal value is output.

Unit_Delay_process : PROCESS (clk, reset)
  BEGIN
    IF reset = '1' THEN
      Unit_Delay_out1 <= to_signed(0, 32);
    ELSIF clk'EVENT AND clk = '1' THEN
      Unit_Delay_out1 <= In1_signed;
    END IF;
  END PROCESS Unit_Delay_process;

Off

Generate clock enable logic. The following VHDL code extract represents a register with a clock enable (enb)

Unit_Delay_process : PROCESS (clk, reset)
  BEGIN
    IF reset = '1' THEN
      Unit_Delay_out1 <= to_signed(0, 32);
    ELSIF clk'EVENT AND clk = '1' THEN
      IF enb = '1' THEN
        Unit_Delay_out1 <= In1_signed;
      END IF;
    END IF;
  END PROCESS Unit_Delay_process;

Exceptions

In some cases, HDL Coder emits clock enables even when Minimize clock enables is selected. These cases are:

• Registers inside Enabled, State-Enabled, and Triggered subsystems.

• Multirate models.

• The coder always emits clock enables for the following blocks:

  • commseqgen2/PN Sequence Generator

  • dspsigops/NCO

    Note:   HDL support for the NCO block will be removed in a future release. Use the NCO HDL Optimized block instead.

  • dspsrcs4/Sine Wave

  • hdldemolib/HDL FFT

  • built-in/DiscreteFir

  • dspmlti4/CIC Decimation

  • dspmlti4/CIC Interpolation

  • dspmlti4/FIR Decimation

  • dspmlti4/FIR Interpolation

  • dspadpt3/LMS Filter

  • dsparch4/Biquad Filter

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

MinimizeClockEnables

Use trigger signal as clock

Enable to use trigger input signal as clock in generated HDL code.

Settings

Default: Off

On

For triggered subsystems, use the trigger input signal as a clock in the generated HDL code.

Off

For triggered subsystems, do not use the trigger input signal as a clock in the generated HDL code.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

TriggerAsClock

Transform non zero initial value delay

Enable this option to optimize Delay blocks with non zero initial condition.

Settings

Default: On

On

Transform Delay blocks with nonzero Initial condition in your Simulink^® model to Delay blocks with zero Initial condition and some additional logic in the generated HDL code.

By using this transformation, HDL Coder can perform optimizations such as sharing, distributed pipelining, and clock-rate pipelining more effectively, and prevent an assertion from being triggered in the validation model.

Off

Do not transform Delay blocks with nonzero Initial condition in your Simulink model.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

TransformNonZeroInitDelay

Multiplier partitioning threshold

Specify the maximum input bit width for multipliers in your design.

Settings

Default: Inf

N, where N is an integer greater than or equal to 2

Partition multipliers so that N is the maximum multiplier input bit width.

To improve hardware mapping results, set the multiplier partitioning threshold to the input bit width of the DSP or multiplier hardware on your target device.

Inf

Do not partition multipliers.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

MultiplierPartitioningThreshold

RAM mapping threshold (bits)

Specify the minimum RAM size for mapping to block RAMs instead of to registers.

Settings

Default: 256

The RAM mapping threshold must be an integer greater than or equal to zero. HDL Coder uses the threshold to determine whether or not to map the following elements to block RAMs instead of to registers:

• Delay blocks

• Persistent arrays in MATLAB Function blocks

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

• RAMMappingThreshold

• UseRAM

• MapPersistentVarsToRAM

Timing controller architecture

Specify whether to generate a reset for the timing controller.

Settings

Default: default

resettable

Generate a reset for the timing controller. If you select this option, the Clock inputs value must be Single.

default

Do not generate a reset for the timing controller.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

TimingControllerArch

Hierarchical distributed pipelining

Specify that retiming be applied across a subsystem hierarchy.

Settings

Default: Off

On

Enable retiming across a subsystem hierarchy. HDL Coder applies retiming hierarchically down, until it reaches a subsystem where DistributedPipelining is off.

Off

Distribute pipelining only within a subsystem.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

• HierarchicalDistPipelining

• DistributedPipelining

Clock-rate pipelining

Insert pipeline registers at the clock rate instead of the data rate for multi-cycle paths in your design.

Settings

Default: On

On

Insert pipeline registers at clock rate for multi-cycle paths.

Off

Insert pipeline registers at data rate for multi-cycle paths.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

• ClockRatePipelining

• Clock-Rate Pipelining

Allow clock-rate pipelining of DUT output ports

For DUT output ports, insert pipeline registers at the clock rate instead of the data rate.

Settings

Default: Off

On

At DUT output ports, insert pipeline registers at clock rate.

Off

At DUT output ports, insert pipeline registers at data rate.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

• ClockRatePipelineOutputPorts

• ClockRatePipelining

• Clock-Rate Pipelining

Preserve design delays

Enable to prevent distributed pipelining from moving design delays.

Settings

Default: Off

On

Prevent distributed pipelining from moving design delays.

Off

Do not prevent distributed pipelining from moving design delays.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

• PreserveDesignDelays

• DistributedPipelining

Adaptive pipelining

Insert adaptive pipeline registers in your design.

Settings

Default: On

On

Insert adaptive pipeline registers in your design. For HDL Coder to insert adaptive pipelines, you must specify the synthesis tool. If your design has multipliers, specify the synthesis tool and the target frequency for adaptive pipeline insertion.

Off

Do not insert adaptive pipeline registers.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

• Adaptive pipelining

• AdaptivePipelining

Distributed pipelining priority

Specify priority for distributed pipelining algorithm.

Settings

Default: Numerical Integrity

Numerical Integrity

Prioritize numerical integrity when distributing pipeline registers.

This option uses a conservative retiming algorithm that does not move registers across a component if the functional equivalence to the original design is unknown.

Performance

Prioritize performance over numerical integrity.

Use this option if your design requires a higher clock frequency and the Simulink behavior does not need to strictly match the generated code behavior. This option uses a more aggressive retiming algorithm that moves registers across a component even if the modified design's functional equivalence to the original design is unknown.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

• DistributedPipeliningPriority

• DistributedPipelining

Adders

Enable to share adders with the resource sharing optimization.

Settings

Default: Off

On

When resource sharing is enabled, share adders with a bit width greater than or equal to Adder sharing minimum bitwidth.

Off

Do not share adders.

Command-Line Information

See Also

• ShareAdders

• AdderSharingMinimumBitwidth

• Resource Sharing

Multipliers

Share multipliers with the resource sharing optimization.

Settings

Default: On

On

When resource sharing is enabled, share multipliers with a bit width greater than or equal to MultiplierSharingMinimumBitwidth. For successfully sharing multipliers, the input fixed-point data types must have the same wordlength. The fraction lengths and signs of the fixed-point data types can be different.

Off

Do not share multipliers.

Command-Line Information

See Also

• ShareMultipliers

• MultiplierSharingMinimumBitwidth

• Resource Sharing

Multiply-Add blocks

Share Multiply-Add blocks with the resource sharing optimization.

Settings

Default: On

On

When resource sharing is enabled, share Multiply-Add blocks with a bit width greater than or equal to Multiply-Add block sharing minimum bitwidth.

Off

Do not share Multiply-Add blocks.

Command-Line Information

See Also

• Resource Sharing

Atomic subsystems

Share atomic subsystems with the resource sharing optimization.

Settings

Default: On

On

When resource sharing is enabled, share atomic subsystems.

Off

Do not share atomic subsystems.

Command-Line Information

See Also

• ShareAtomicSubsystems

• Resource Sharing

MATLAB Function blocks

Share MATLAB Function blocks with the resource sharing optimization.

Settings

Default: On

On

When resource sharing is enabled, share MATLAB Function blocks.

Off

Do not share MATLAB Function blocks.

Command-Line Information

See Also

• ShareMATLABBlocks

• Resource Sharing

Floating-point IPs

Share floating-point IP blocks in the target hardware with the resource sharing optimization.

Settings

Default: On

On

When you enable resource sharing, HDL Coder shares floating-point IP blocks. The number of floating-point IP blocks that get shared depends on the SharingFactor that you specify for the subsystem.

Off

Do not share floating-point IP blocks.

Command-Line Information

See Also

• Resource Sharing

• ShareFloatingPointIP

Adder sharing minimum bitwidth

Minimum bit width for shared adders.

To share only larger adders with the resource sharing optimization, specify the minimum adder bit width.

Settings

Default: 0

0, 1

No minimum bit width for shared adders.

N, where N is an integer greater than 1

When resource sharing and adder sharing are enabled, share adders with a bit width greater than or equal to N.

Command-Line Information

See Also

• AdderSharingMinimumBitwidth

• ShareAdders

• Resource Sharing

Multiplier sharing minimum bitwidth

Minimum bit width for shared multipliers.

To share only larger multipliers with the resource sharing optimization, specify the minimum multiplier bit width.

Settings

Default: 0

0, 1

No minimum bit width for shared multipliers.

N, where N is an integer greater than 1

When resource sharing and multiplier sharing are enabled, share multipliers with a bit width greater than or equal to N.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

• MultiplierSharingMinimumBitwidth

• ShareMultipliers

• Resource Sharing

Multiplier promotion threshold

Maximum word-length by which HDL Coder promotes a multiplier for sharing with other multipliers.

To share smaller multipliers with other larger multipliers by using the resource sharing optimization, specify the multiplier promotion threshold.

Settings

Default: 0

0

No difference in word-length between the multipliers. In other words, HDL Coder shares multipliers that have the same word-lengths.

N, where N is an integer greater than 0

Maximum word-length by which HDL Coder promotes a multiplier for sharing with other multipliers. HDL Coder promotes and shares multipliers with different word-lengths, if the difference in word-lengths is less than or equal to N.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

• MultiplierPromotionThreshold

• ShareMultipliers

• Resource Sharing

Multiply-Add block sharing minimum bitwidth

Minimum bit width for shared Multiply-Add blocks.

To share only larger Multiply-Add blocks with the resource sharing optimization, specify the minimum multiplier bit width.

Settings

Default: 0

0, 1

No minimum bit width for shared Multiply-Add blocks.

N, where N is an integer greater than 1

When resource sharing and Multiply-Add block sharing are enabled, share Multiply-Add blocks with a bit width greater than or equal to N.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

• Resource Sharing