hdlsetuptoolpath
FunctionTo use HDL Coder™ with one of the supported third-party
FPGA synthesis tools, add the tool to your system path using the
function.
Add the tool to your system path before opening the HDL Workflow
Advisor. If you already have the HDL Workflow Advisor open, see Add Synthesis Tool for Current HDL Workflow Advisor Session.hdlsetuptoolpath
Simulink to HDL Workflow
At the MATLAB® command line, use the
function
to add the synthesis tool.hdlsetuptoolpath
In the HDL Workflow Advisor, in the Set Target > Set Target Device and Synthesis Tool step, to the right of Synthesis tool, click Refresh.
The synthesis tool is now available.
MATLAB to HDL Workflow
At the MATLAB command line, use the
function
to add the synthesis tool.hdlsetuptoolpath
In the HDL Workflow Advisor, in the Select Code Generation Target step, to the right of Synthesis tool, click Refresh list.
The synthesis tool is now available.
To check your Altera® Quartus synthesis tool setup in MATLAB, try launching the tool with the following command:
!quartus
To check your Xilinx® Vivado® synthesis tool setup in MATLAB, try launching the tool with the following command:
!vivado
To check your Xilinx ISE synthesis tool setup in MATLAB, try launching the tool with the following command:
!ise
For supported tool versions, see Third-Party Synthesis Tools and Version Support.
To set up ModelSim®, Questa®, or Incisive® for HDL simulation, or for cosimulation with HDL Verifier™, see HDL Simulator Startup.
MATLAB to HDL Workflow
Set up your simulation tool.
In the HDL Workflow Advisor, in the HDL Verification > Verify with HDL Test Bench task, click Refresh list.
The simulation tool is now available.
To generate ModelSim simulation scripts for a design containing Xilinx System Generator blocks, you must:
Have compiled Xilinx simulation libraries.
Specify the path to your compiled libraries.
To generate ModelSim simulation scripts, you must have the following compiled Xilinx simulation libraries for your EDA simulator and target language:
unisim
simprim
xilinxcorelib
To learn how to compile these libraries, refer to the Xilinx documentation.
For Vivado, see compile_simlib
.
For ISE, see compxlib
.
Specify the path to your compiled Xilinx simulation libraries
by setting the XilinxSimulatorLibPath
parameter
for your model.
For example, you can use hdlset_param
to
set XilinxSimulatorLibPath
:
libpath = '/apps/Xilinx_ISE/XilinxISE-13.4/Linux/ISE_DS/ISE/vhdl/ mti_se/6.6a/lin64/xilinxcorelib'; hdlset_param (bdroot, 'XilinxSimulatorLibPath', libpath);
To generate code for a design containing both Altera DSP Builder and Simulink® blocks, you must open MATLAB with Altera DSP Builder. For details, refer to the Altera DSP Builder documentation.
To map your design to an Altera or a Xilinx FPGA simulator library:
Use Xilinx LogiCORE® IP Floating-Point Operator v5.0 or Altera floating-point megafunction IP cores.
Specify the compiled simulation library and the target
language for your EDA simulator. Use XilinxCoreLib
simulation
library for Xilinx LogiCORE IP and the EDA simulation library
compiler for Altera megafunction IP.
To learn how to compile this library, refer to the Xilinx compxlib
documentation
.
Specify the path to your compiled Altera or Xilinx simulation
libraries. Altera provides the simulation model files in \quartus\eda\sim_lib folder. Set the SimulationLibPath
parameter
for your DUT.
For example, you can use hdlset_param
to
set SimulationLibPath
:
myDUT = gcb; libpath = '/apps/Xilinx_ISE/XilinxISE-13.4/Linux/ISE_DS/ISE/vhdl/ mti_se/6.6a/lin64/xilinxcorelib'; hdlset_param (myDUT, 'SimulationLibPath', libpath);
You can also specify the simulation library path from the HDL Code Generation > Test Bench pane in the Configuration Parameters dialog box.
HDL Coder locates and uses a supported installed compiler. For most platforms, a default compiler is supplied with MATLAB. For a list of supported compilers, see Supported Compilers.