Specify the target frequency for multiple features and workflows
N
Default: 0
This setting is the target frequency in MHz for multiple features and workflows that HDL Coder™ supports. The supported features are:
FPGA floating-point target library mapping: Specify
the target frequency that you want the IP to achieve when you use ALTERA
MEGAFUNCTION (ALTERA FP FUNCTIONS). If you do not specify
the target frequency, HDL Coder sets the target frequency to a
default value of 200 MHz.
Adaptive pipelining: If your design uses multipliers,
specify the synthesis tool and the target frequency. Based on these
settings, HDL Coder estimates the number of pipelines that can
be inserted to improve area and timing on the target platform. If
you do not specify the target frequency, HDL Coder uses a target
frequency of 0 MHz and cannot insert any pipelines.
To use this parameter, on the Configuration Parameters dialog box, in the HDL Code Generation > Target and Optimizations pane, for Target Frequency (MHz), enter an integer. You can also set the target frequency by using the Target Frequency (MHz) setting in the Set Target Frequency task in the HDL Workflow Advisor.
Specify the target frequency for these workflows:
Generic ASIC/FPGA: To specify
the target frequency that you want your design to achieve. HDL Coder generates
a timing constraint file for that clock frequency. It adds the constraint
to the FPGA synthesis tool project that you create in the Create
Project task. If the target frequency is not achievable,
the synthesis tool generates an error.
IP Core Generation: To
specify the target frequency for HDL Coder to modify the clock
module setting in the reference design to produce the clock signal
with that frequency. Enter a target frequency value that is within
the Frequency Range (MHz). If you do not specify
the target frequency, HDL Coder uses the Default (MHz) target
frequency.
Simulink Real-Time FPGA I/O:
For Speedgoat boards that are supported with Xilinx ISE,
specify the target frequency to generate the clock module to produce
the clock signal with that frequency.
The Speedgoat boards that are supported with Xilinx
Vivado use the IP Core Generation workflow
infrastructure. Specify the target frequency for HDL Coder to
modify the clock module setting in the reference design to produce
the clock signal with that frequency. Enter a target frequency value
that is within the Frequency Range (MHz). If
you do not specify the target frequency, HDL Coder uses the Default
(MHz) target frequency.
FPGA Turnkey: To generate
the clock module to produce the clock signal with that frequency.
To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.