The HDL Coder™ software supports several optimizations, block implementations, and options that introduce discrete delays into the model, with the goal of more efficient hardware usage or achieving higher clock rates. Examples include:
Optimizations: Optimizations such as output pipelining, streaming, or resource sharing can introduce delays.
Cascading: Some blocks support cascade implementations, which introduce a cycle of delay in the generated code.
Block implementations: Some block implementations inherently introduce delays in the generated code. Resolve Numerical Mismatch with Delay Balancing discusses one such implementation.
When optimizations or block implementation options introduce delays along the critical path in a model, the numerics of the original model and generated model or HDL code can differ because equivalent delays are not introduced on other, parallel signal paths. Manual insertion of compensating delays along the other paths is possible, but is error prone and does not scale well to large models with many signal paths or multiple sample rates.
To help you solve this problem, HDL Coder supports delay balancing. When you enable delay balancing and the coder detects introduction of new delays along one path, the coder inserts matching delays on the other paths. When delay balancing is enabled, the generated model is functionally equivalent to the original model.
You can set delay balancing for an entire model. For finer control, you can also set delay balancing for subsystems within the top-level DUT subsystem.
Use the following makehdl properties to
set delay balancing for a model:
BalanceDelays: By default, model-level
delay balancing is enabled, and subsystems within the model inherit
the model-level setting. To learn how to set delay balancing for a
model, see BalanceDelays.
GenerateValidationModel: By default,
validation model generation is disabled. When you enable delay balancing,
generate a validation model to view delays and other differences between
your original model and the generated model. To learn how to enable
validation model generation, see GenerateValidationModel.
For example, the following commands generate HDL code with delay balancing and generate a validation model.
dut = 'ex_rsqrt_delaybalancing/Subsystem'; makehdl(dut,'BalanceDelays','on','GenerateValidationModel','on');
For more information about the validation model, see Validation Model.
You can disable delay balancing for an entire model, or disable a subsystem within the top-level DUT subsystem. For example, if you do not want to balance delays for a control path, you can put the control path in a subsystem, and disable delay balancing for that subsystem.
To disable delay balancing for a subsystem within the top-level DUT subsystem, disable delay balancing at the model level. When you disable delay balancing for the model, the validation model does not compensate for latency inserted in the generated model due to optimizations or block implementations. The validation model can therefore show mismatches between the original model and generated model.
To disable delay balancing for a subsystem within the top-level DUT subsystem:
Disable delay balancing for the model.
Enable delay balancing for the top-level DUT subsystem.
Disable delay balancing for a subsystem within the DUT subsystem.
To learn how to set delay balancing for a subsystem, see Set Delay Balancing For a Subsystem.
The following blocks and subsystems do not support delay balancing:
Triggered Subsystem
Atomic Subsystem
HDLCosimulation
Data Type Duplicate
Decrement To Zero
Frame Conversion
Ground
FFT HDL Optimized
LMS Filter
Model Reference
To VCD File
Magnitude-Angle to Complex
The following block implementations do not support delay balancing:
hdldefaults.ConstantSpecialHDLEmission
hdldefaults.NoHDL
HDL Coder does not support delay balancing, if:
There are multiple instances of an Atomic Subsystem in different conditional subsystems.
The BalanceDelays block
property for all instances of an Atomic Subsystem or Model
Reference resolves to a different value.
To fix this error, disable BalanceDelays for
all instances of the Atomic Subsystem or Model
Reference.
The block is inside a conditional subsystem and has pipeline delays.
Delays are introduced in a feedback loop, and HDL Coder cannot balance the path delays. For example, if you apply clock-rate pipelining inside a feedback loop, HDL Coder introduces a delay at the clock-rate, and can cause delay balancing to fail.
To reduce the number of clock-rate delays, increase the Oversampling factor.
The sample time is not discrete, or the ratio of sample times of the fastest to the slowest rate is too large.
A subsystem with BlackBox Architecture has
the ImplementationLatency block property set
to a negative value.
To fix this error, for ImplementationLatency, enter a nonnegative integer.
If delay balancing is unsuccessful, hdlcoder.optimizeDesign cannot
optimize the generated HDL code.
To see the delay balancing information, select the Delay Balancing section of the optimization report when you generate the optimization report for each subsystem, model reference, or MATLAB Function block.
Success: Lists the pipeline latency and phase delay at the output ports that shows the number of pipelines added at the output ports to match the delays.
Failure: Identifies which criterion was violated and displays the link to the block or subsystem in the Simulink® model that caused delay balancing to fail.
Latency changes.
See also Optimization Report.