In R2016b, if you use single-precision data types in your Simulink^® model, HDL Coder™ can generate target-independent HDL code without converting to fixed point. You can deploy the generated code on any generic ASIC or FPGA platform.

In your Simulink model:

• You can have a combination of integer, fixed-point, and floating-point operations. By using Data Type Conversion blocks, you can perform conversions between single-precision and fixed-point data types.

• If your design does not use denormal numbers, you can specify that HDL Coder does not have to add the additional logic to check for denormal numbers, which improves area on the target hardware platform.

• By using the latency strategy setting, customize the latency of the native floating-point library.

The generated code:

• Complies with the IEEE-754 standard of floating-point arithmetic.

• Does not require floating-point processing units or hard floating-point DSP blocks on the target ASIC or FPGA.

When you verify the generated code, use HDL testbench to check for floating-point tolerance based on relative error or ulp error, and to ensure accuracy of your design with Simulink.

To specify native floating-point support, in the Configuration Parameters dialog box, on the HDL Code Generation > Global Settings > Floating Point Target tab, for Library, specify NATIVE FLOATING POINT.

For more information, see Native Floating Point.

You can now specify adaptive pipelining for your Simulink model, or for an individual subsystem in your Simulink model, to improve area and timing on the target FPGA device. To insert adaptive pipelines, specify the synthesis tool and the target frequency. HDL Coder inserts the required number of pipelines for potential area and timing improvements for these blocks:

• Lookup Table

• Product, Gain, and Multiply-Add

• Rate Transition and Downsample

You can enable adaptive pipelining by using the AdaptivePipelining property from the command line, or by using the AdaptivePipelining HDL block property for the Subsystem. See also Adaptive Pipelining.

HDL Coder displays a report that shows the adaptive pipelining status and whether HDL Coder successfully inserted pipeline registers. For more information, see Optimization Report.

If you have DSP System Toolbox™, by using the Logic Analyzer visualization tool, you can view the transitions of signals. Use the Logic Analyzer to:

• Debug and analyze models.

• Trace and correlate many signals simultaneously.

• Detect and analyze timing violations.

• Trace system execution.

You can now generate HDL code from the Discrete FIR Filter block when using frame input. Set Input processing to Columns as channels (frame based). Then, right-click the block and open HDL Code > HDL Block Properties. Set the Architecture to Frame Based. The block accepts vector input data, where each element of the vector represents a sample in time. The coder implements a parallel HDL architecture for the filter. See Discrete FIR Filter.

The Delay block also supports HDL code generation with frame input data. Set Input processing to Columns as channels (frame based). The block accepts vector input data, where each element of the vector represents a sample in time.

This capability increases throughput in hardware designs.

In R2016b, when your synthesis tool is Xilinx^® Vivado^®, HDL Coder can generate an IP core with an AXI4-Stream Video interface for your video algorithm. To generate an IP core, model your video algorithm by using the streaming pixel protocol. Then, in the Target platform interface table map the pixel data and pixel control bus ports to the AXI4-Stream Video Master or AXI4-Stream Video Slave interfaces.

You can integrate the generated IP core into the Default video system reference design or your own custom video reference design.

For more information, see Model Design for AXI4-Stream Video Interface Generation.

For vector input data, the HDL-optimized FFT now supports bit-reversed input with natural order output. For scalar input data, you can select any input order with any output order. The default is natural order input with bit-reversed output.

This change affects these blocks and System objects:

• FFT HDL Optimized

• IFFT HDL Optimized

• dsp.HDLFFT

• dsp.HDLIFFT

The Generate HDL Code for High Throughput Signal Processing example shows how to design a Polyphase Filter Bank to achieve gigasample per second (GSPS) data rates in the generated HDL implementation. The model uses the FFT HDL Optimized block with vector input.

You can now generate HDL code from the Discrete FIR Filter block when you configure the block to have an external reset port.

In your Simulink model, you can now use an array of buses for HDL code generation.

When your Simulink model uses an array of buses, in the generated code, HDL Coder expands the array of buses into the corresponding scalars. For more information, see Generating HDL Code for Subsystems with Array of Buses.

To learn more about array of buses and supported blocks, see Combine Buses into an Array of Buses.

You can specify synchronous hardware behavior and generate cleaner HDL code for a Resettable Subsystem with the State Control block. If you specify synchronous hardware behavior, the HDL code uses fewer hardware resources, because HDL Coder does not generate bypass registers.

The Resettable Synchronous Subsystem block is now available as part of the HDL Subsystems block library in HDL Coder. The Resettable Synchronous Subsystem block uses the synchronous hardware behavior of the State Control block with the Resettable Subsystem block.

For an example that shows how to use the Resettable Synchronous Subsystem block, see Resettable Subsystem Support in HDL Coder™.

In the Lookup Tables block library in HDL Coder, the Sine HDL Optimized and Cosine HDL Optimized blocks replace the Sine and Cosine blocks respectively. You can still use the Sine and Cosine blocks from the Lookup Tables block library in Simulink for HDL code generation.

The new blocks are optimized for area and speed because you can configure them with Lookup Tables that have an exact power of two as its number of elements. In the generated code, the Lookup Tables precede a register without reset so that they map efficiently to RAM blocks on the target hardware platform.

Starting in R2016b, HDL Coder supports configuration set management workflow on the Model Explorer, or from the command line. You can create an active configuration set with the preferred HDL Configuration Parameters on a standard Simulink model, and export and copy this configuration set for Simulink models that you create.

Previously, you created a configuration set for each Simulink model, and ensured that the configuration set had similar contents for all your Simulink models.

You can now specify the VHDL architecture name in the Configuration Parameters dialog box.

• Commonly Used Parameters tab: HDL Code Generation > Global Settings > General tab.

• All Parameters tab: Search for VHDLArchitectureName.

Starting in R2016b, when generating code for RAM blocks in your Simulink model, HDL Coder adds parameters in Verilog and generics in VHDL for the RAM address and data widths. This means that HDL Coder generates only one generic RAM file for RAM blocks that differ in address widths, data widths, or both.

Starting with R2016b, you can manage and define tunable parameters in a Simulink data dictionary for HDL code generation.

To learn more about data dictionary, see What Is a Data Dictionary?.

When your Simulink model contains a Stateflow^® Chart that uses comments, HDL Coder generates comments in the HDL code. For example, consider this Moore Stateflow Chart in your Simulink model.

When you generate Verilog code from the model, HDL Coder displays the comments in the Stateflow Chart inline beside the corresponding Stateflow object.

 always @(is_AL_Chart) begin
    out0_1 = 8'sb00000000;
    case ( is_AL_Chart)
      is_AL_Chart_IN_init :
        begin
          // This is comment 1
          out0_1 = 8'sb00000000;
        end
      default :
        begin
          // This is comment 2
          out0_1 = 8'sb00001010;
        end
    endcase
  end

 always @(is_AL_Chart) begin
    out0_1 = 8'sb00000000;
    case ( is_AL_Chart)
      is_AL_Chart_IN_init :
        begin
          out0_1 = 8'sb00000000;
        end
      default :
        begin
          out0_1 = 8'sb00001010;
        end
    endcase
  end

When mapping your Simulink model to floating-point libraries, you can specify the tolerance check when you generate the testbench.

For operators such as trigonometric sine and cosine, there can be small rounding errors or numeric differences with the correct rounding range of values that the IEEE-754 standard specifies. To check for numerical accuracy in the generated testbench by using HDL testbench, specify the floating-point tolerance check.

You can perform the floating-point tolerance check based on the relative error or ulp error.

• relative error: Relative error is the rounding error when approximating a nonzero real number. By default, the tolerance value is 1e-07. You can specify a tolerance value less than or equal to 1e-07.

• ulp error: ulp (unit in the last place) is the gap between two floating-point numbers nearest x, even if x is one of the numbers. By default, the tolerance value is zero. You can specify a tolerance value greater than or equal to zero.

To check for floating-point tolerance, in the Configuration Parameters dialog box, on the Configuration section of HDL Code Generation > Test Bench tab, for Floating point tolerance check based on, specify relative error or ulp error, and enter the Tolerance Value.

For more information, see FPToleranceValue and FPToleranceStrategy.

In R2016b, HDL Coder supports mask parameters at the DUT as generic ports for HDL code generation.

Delay Balancing Report

HDL Coder now displays the path delay balancing information in the Delay Balancing section of the Optimization Report. Previously, the Optimization Report displayed the delay balancing information in the Path Delay Summary subsection of the Streaming and Sharing report.

See also Optimization Report.

Shift Operators in Resource Report

The High-level Resource Report Summary shows the number of Static Shift operators and Dynamic Shift operators. The Detailed Report shows the number of static left shift, static right shift, dynamic left shift, and dynamic right shift operators.

The HDL Coder documentation provides a comprehensive list of coding standard rules with recommendations for each of the rules. The coding standard rules fall under three categories:

• Basic Coding Practices: Checks for conformance of modeling constructs with general naming conventions and basic coding guidelines. See Basic Coding Practices.

• RTL Description Techniques: Checks for conformance with RTL description rules and guidelines. See RTL Description Techniques.

• RTL Design Methodology Guidelines: Includes guidelines for creating and using function libraries, and test facilitation design. See RTL Design Methodology Guidelines.

To learn more about HDL coding standards, see HDL Coding Standards and HDL Coding Standard Report.

You can now call a System object™ with arguments, as if it were a function, instead of using the step method to perform the operation defined by the object. The step method continues to work. This capability improves the readability of scripts and functions that use many different System objects.

For example, if you create a hdl.RAM System object named ramsingle, and then call the System object as a function with that name:

ramsingle = hdl.RAM('RAMType','Single port', ...
    'WriteOutputValue','Old data');
ramsingle(x)

The equivalent operation with the step method is:

ramsingle = hdl.RAM('RAMType','Single port', ...
    'WriteOutputValue','Old data');
step(ramsingle,x)

When the step method has the System object as its only argument, the function equivalent has no arguments. You must call this function with empty parentheses. For example, step(sysobj) and sysobj() perform equivalent operations.

The Diagnostic Viewer in Simulink now includes an option to suppress certain diagnostics. You can suppress warnings for specific objects in your model. In the Diagnostic Viewer, click the Suppress button next to the warning to suppress the warning from the specified source. You can restore the warning from the source by clicking Restore.

You can also control the suppressions from the command line. To view the existing suppressions on the model, use the Simulink.getSuppressedDiagnostics function.

Suppressed = Simulink.getSuppressedDiagnostics('myModel')

Suppressed = 

  SuppressedDiagnostic with properties:

            Source: 'myModel/Data Type Conversion'
                Id: 'SimulinkFixedPoint:util:Saturationoccurred'
    LastModifiedBy: ''
          Comments: ''
      LastModified: '2016-Apr-26 10:31:22'

Simulink.suppressDiagnostic('myModel/Data Type Conversion1', 'SimulinkFixedPoint:util:Overflowoccurred')
Suppressed

Suppressed = 

  1×2 SuppressedDiagnostic array with properties:

    Source
    Id
    LastModifiedBy
    Comments
    LastModified

Simulink.restoreDiagnostic('myModel/Data Type Conversion1', 'SimulinkFixedPoint:util:Overflowoccurred')

Previously, in the HDL Workflow Advisor Fixed-Point Conversion task, the HDL Coder app displayed logs and report links for range analysis, fixed-point conversion, and verification on separate tabs that were placed on top of each other. To see a hidden tab, you opened a menu and selected the tab.

In R2016b, the app displays logs and report links for range analysis and fixed-point conversion on the Output tab. It displays logs and report links for verification on the Verification Output tab. These tabs are next to each other so that you can more easily find them.

Subsystem level control of clock-rate pipelining

You can now specify clock-rate pipelining for individual subsystems in your Simulink model. With this optimization, you can selectively apply clock-rate pipelining to subsystems in your model design that are on the critical path, and improve timing.

To disable clock-rate pipelining for an individual subsystem, in HDL Block Properties for the subsystem, set ClockRatePipelining to off.

To learn more about the HDL block property, see ClockRatePipelining.

Optimization of Downsample block with nonzero offset

In R2016b, when you have a Downsample block with a nonzero Sample offset at the boundary of a clock-rate pipelining region, HDL Coder does not introduce the additional latency or generate a Rate Transition block. This optimization improves timing and area.

For more information, see Clock-Rate Pipelining.

Sharing of multipliers with different word-lengths

HDL Coder now shares Product blocks and Gain blocks in your Simulink model that have different word-lengths. This optimization shares more multipliers, which saves area on the target platform.

To share multipliers that have different word-lengths, in the Configuration Parameters dialog box, on the HDL Code Generation > Target and Optimizations > Resource Sharing tab, specify the Multiplier promotion threshold. The Multiplier promotion threshold is the maximum word-length by which HDL Coder promotes a multiplier for sharing with other multipliers.

Previously, for successful resource sharing, you used Product blocks or Gain blocks with the same word-length.

See also MultiplierPromotionThreshold and Resource Sharing.

Sharing of floating-point IP

HDL Coder now shares floating-point IP blocks in the target hardware based on the SharingFactor that you specify. This optimization saves area on the target hardware by sharing more floating-point IP blocks.

If you do not want to share floating-point IP blocks, in the Configuration Parameters dialog box, on the Resource Sharing tab, clear Floating-point IPs.

See also ShareFloatingPointIP.

Starting in R2016b, if delay balancing is unsuccessful, HDL Coder generates an error. To see the block or subsystem in your Simulink model that caused delay balancing to fail, in the Delay Balancing section of the Optimization report, click the link to that block or subsystem.

Compatibility Considerations

Previously, HDL Coder reported delay balancing failures as warnings. Now, if you load a pre-R2016b model for which delay balancing was unsuccessful, HDL Coder generates an error.

To learn more about possible reasons for delay balancing to fail, see Delay Balancing.

In the generated code, HDL Coder now replaces a Delay block that has nonzero initial condition in your Simulink model with a Delay block that has zero initial condition and some additional logic. With this replacement, optimizations such as sharing, distributed pipelining, and clock-rate pipelining can work more effectively, and prevent an assertion from being triggered in the validation model.

To disable this optimization, in the Configuration Parameters dialog box, on the HDL Code Generation > Target and Optimizations > General tab, clear Transform non zero initial value delay.

For more information, see TransformNonZeroInitDelay.

Starting with R2016b, to initialize the registers, you can use the no-reset registers initialization setting to specify Generate an external script, Do not initialize, or Generate initialization inside module. When you select Generate initialization inside module, in Verilog, HDL Coder initializes the registers by using an initial block in each module. In VHDL, HDL Coder initializes the registers as part of the signal declaration statements.

Previously, if you had Delay blocks in your Simulink model with ResetType set to None, HDL Coder generated an external script to initialize the Delay blocks for ModelSim^® simulation.

The no-reset registers initialization setting is available in the Configuration Parameters dialog box, on the HDL Code Generation > Global Settings > Coding style tab.

To learn more, see NoResetInitializationMode.

In R2016b, you can flatten masked subsystems and library blocks that contain Lookup Tables to enable further optimizations and file reduction.

You can customize the floating-point target IP settings by using the floating-point target configuration that you specify for the library. When you customize the IP settings, you can choose from different combinations of IP names and data types, and specify the latency or the target frequency that you want the IP to achieve. You can customize the IP settings from:

• Floating Point Target tab in Configuration Parameters dialog box: When you specify an Altera^® or Xilinx FPGA floating-point library, specify your custom settings in the IP Settings section.

• Command-line interface: By using the hdlcoder.createFloatingPointTargetConfig class, you can create a floating-point target configuration object for a given FPGA floating-point library or the HDL Coder native floating-point. In the IPConfig property of this object, use the customize function to customize the IP settings.

For more information, see Customize Floating-Point IP Configuration.

For FPGA floating-point target library mapping, HDL Coder supports these Simulink blocks and block modes:

• MinMax block.

• Unary Minus block.

• Add block with - ports.

See also HDL Coder Support for FPGA Floating-Point Library Mapping.

You can use a new Default video system (requires HDMI FMC module) reference design with these target platforms:

• Xilinx Zynq ZC702 evaluation kit

• Xilinx Zynq ZC706 evaluation kit

• ZedBoard

You must have Embedded Coder^® and the Computer Vision System Toolbox™ Support Package for Xilinx Zynq^®-Based Hardware.

For your custom reference design, by using the hdlcoder.ReferenceDesign class, specify your own custom parameters and custom callback functions. Therefore, you can customize the settings that HDL Coder uses to create the project, generate the software interface model, and build the FPGA bitstream.

The IP Core Generation workflow has these enhancements:

• The Set Target Interface task is split into two tasks. One task is the original Set Target Interface, and the other task is a new Set Target Reference Design. In the Set Target Reference Design task, you can specify the parameters and supported tool version for the target reference design.

  The reference design setting has moved from the Set Target Interface task to the Set Target Reference Design task.

• The new task Set Target Frequency means that you can specify the Target Frequency (MHz) for your design.

To learn more, see Define Custom Parameters and Callback Functions for Custom Reference Design and hdlcoder.ReferenceDesign.

Compatibility Considerations

In the Generate Software Interface Model task, the Add IP core device driver check box has been removed. To add the device driver, in the task Program Target Device, specify a new Download Programming method. The Download Programming method copies the generated FPGA bistream, device tree, and system initialization scripts to the SD card on the Zynq board, and keeps the bitstream on the SD card persistently.

The reference design names no longer contain a tool version number. If you load a pre-R2016b model that was saved with a reference design containing a version number in its name, and then open the HDL Workflow Advisor, HDL Coder generates a warning. To avoid this warning, select the reference design that does not have the tool version number, and save the model.

You can use the IP Core Generation workflow to generate an HDL IP core for any supported Xilinx or Altera FPGA device. You can integrate the generated IP core into the Default system reference design, or create a custom board and reference design definition for your own FPGA board.

• With a new task Set Target Frequency, you can specify the Target Frequency (MHz) for your design.

• If the target device does not have an embedded ARM processor, there is no longer the Generate Software Interface Model task.

To learn more, see IP Core Generation Workflow for Standalone FPGA Devices.

You can target the following FPGA boards for the IP core generation workflow:

• Xilinx Kintex-7 KC705 development board

• Arrow DECA MAX 10 FPGA evaluation kit

For examples that show how to target the FPGA boards, see Using IP Core Generation Workflow with Xilinx FPGA Boards: Xilinx Kintex-7 KC705.

By using the Target Frequency (MHz) setting in the Target and Optimizations pane in the Configuration Parameters dialog box, you can specify the target frequency for:

• FPGA floating-point target library mapping: Specify the target frequency that you want the IP to achieve when you use ALTERA MEGAFUNCTION (ALTERA FP FUNCTIONS).

• Adaptive pipelining: Specify the target frequency for HDL Coder to insert required number of pipelines to improve area and timing on the target platform.

Previously, you specified the target frequency for floating-point library mapping in the Configuration Parameters dialog box, on the HDL Code Generation > Global Settings > Floating Point Target tab.

By using the new Set Target Frequency task in the HDL Workflow Advisor, you can now specify the target frequency for the following workflows:

• Generic ASIC/FPGA

• IP Core Generation

From the command line, use the TargetFrequency property to save the target frequency on the model.

For the new Speedgoat boards, the Simulink Real-Time FPGA I/O workflow supports Xilinx Vivado by using the IP Core Generation workflow.

See also IP Core Generation Workflow for Speedgoat Boards.

You can target the Speedgoat IO333–325K board with Xilinx Kintex7 for the Simulink Real-Time FPGA I/O workflow.

In the Configuration Parameters dialog box, on the HDL Code Generation pane, HDL Coder has a new Target and Optimizations pane where you can specify the target device and optimization settings.

• Parameters that were previously in the General, Pipelining, and Resource Sharing sections of the Optimization tab of Global Settings pane have moved to a General tab, a Pipelining tab, and a Resource Sharing tab respectively in the Optimizations section of Target and Optimizations pane.

• In the Target and Optimizations pane, you now specify the target device settings in the Tool and Device section and the Target Frequency in the Objectives section respectively.

For more information, see HDL Code Generation Pane: Target and Optimizations.

HDL Coder has been tested with:

• Xilinx Vivado Design Suite 2015.4

• Altera Quartus II 15.1

For a list of supported third-party tools and hardware, see Supported Third-Party Tools and Hardware.

In the Configuration Parameters dialog box, on the HDL Code Generation pane, when you select Generate resource utilization report and generate HDL code, HDL Coder displays a link to the Code Generation report. If you happen to close the report after code generation, you can click the link to open the report from the MATLAB^® Command Window.

With the State Control block, you can toggle a subsystem between the default Simulink reset and enable behavior and the synchronous hardware reset and enable behavior. How you set the State Control block affects blocks within the subsystem that have state and have reset or enable ports.

If you specify synchronous hardware behavior, the HDL code is cleaner and requires fewer resources because HDL Coder does not generate bypass registers for enabled subsystems or multiplexers for blocks with reset ports.

To toggle a subsystem between synchronous hardware behavior and default Simulink behavior, add a State Control block to the subsystem:

• For synchronous hardware behavior, in the State Control block, set State control to Synchronous.

• For default Simulink behavior, in the State Control block, set State control to Classic.

The State Control, Enabled Synchronous Subsystem, and Synchronous Subsystem blocks are available as part of the HDL Subsystems block library in HDL Coder. The Synchronous Subsystem and Enabled Synchronous Subsystem blocks use the synchronous hardware behavior of the State Control block with the Subsystem and Enabled Subsystem blocks respectively.

Use the State Control block with Simulink, DSP System Toolbox, Communications System Toolbox™, or Vision HDL Toolbox™ blocks that support HDL code generation.

For more information, see State Control and Synchronous Subsystem Behavior with the State Control Block.

You can increase the throughput of the FFT and IFFT calculation by using vector input and output ports. The internal algorithm computes the FFT or IFFT of each vector element in parallel.

The FFT implementation is now a Radix 2^2 architecture which improves performance for vector input. The table compares hardware implementation resources between the old Radix 2 architecture and the new Radix 2^2 architecture.

This change affects these blocks and System objects:

• FFT HDL Optimized

• IFFT HDL Optimized

• dsp.HDLFFT

• dsp.HDLIFFT

HDL Coder can now map your Simulink model to Altera floating-point IP (ALTERA FP FUNCTIONS) at the target frequency that you specify.

Previously, when mapping to Altera megafunction IP (ALTFP) or Xilinx LogiCORE^® IP, you could specify only whether to optimize the Simulink model for minimum or maximum latency and for speed or area.

For more information, see FPGA Floating-Point Library Mapping and TargetFrequency.

Compatibility Considerations

Previously, you chose the floating-point target library by selecting the Set Target Library (for floating-point synthesis support) check box from the HDL Workflow Advisor.

You now specify the floating-point target library from the HDL Code Generation > Global Settings > Floating Point Target tab in the Model Configuration Parameters dialog box.

HDL Coder can now share multiply and gain blocks that have the same word length but different fraction lengths and different signs. This optimization reduces the resource utilization by sharing more multipliers and gain operations.

Previously, the word length, fraction length, and signs of the multiply or gain blocks had to be the same.

See Requirements and Limitations for Resource Sharing in Resource Sharing.

Reduce test bench generation and simulation time, especially when using large data sets. When you call the makehdltb function, set the GenerateSVDPITestBench property. The coder generates a DPI component for your entire Simulink model, including your DUT and data sources. Your entire model must support C code generation with Simulink Coder™. The coder generates a SystemVerilog test bench that compares the output of the DPI component with the output of the HDL implementation of your DUT. The tool also generates a build script for your simulator. You can specify 'ModelSim', 'VCS', or 'Incisive'.

makehdltb(gcb,'GenerateSVDPITestBench','ModelSim','GenerateHDLTestbench','off')

You can use the HDL Workflow Command Line Interface (CLI) to script the entire Simulink Real-Time™ FPGA I/O workflow.

To create the script to configure your design using the HDL Workflow Advisor, generate a target hardware bitstream or project from your Simulink model, and then export a script. Run the exported script, which contains HDL Workflow CLI commands, to replicate your HDL Workflow Advisor settings and generate the same target hardware bitstream or project.

The Code Generation Report has these enhancements:

• A new Code Interface Report shows the DUT input and output port names, data types, and bit widths.

• The High-level Resource Report shows the number of 1-bit registers and I/O bits. It includes resource usage for model references.

  See Code Interface Report and High-level Resource Report in Resource Utilization Report.

• For each group of streamed or shared blocks, the Sharing and Streaming report provides more details:

  • For shared blocks, the report shows the resource type, block word length, number of blocks in the group, and a traceability link to the blocks in the original model and generated model. It includes a Highlight shared resources and diagnostics link to highlight in the original model and generated model the shared blocks and blocks that are barriers to resource sharing.

  • For streamed blocks, the report links to the group of streamed blocks and shows the streaming factor. It includes a Highlight streaming groups and diagnostics link to highlight in the original model and generated model the streamed blocks and blocks that are barriers to streaming.

    See Streaming and Sharing Report in Optimization Report.

If you use the HDL Coder app to convert your MATLAB code to fixed-point code and propose types based on simulation ranges, the app shows code coverage results. In previous releases, the app showed the coverage as a percentage. In R2016a, the app shows the coverage as a line execution count.

See Code Coverage in Automated Fixed-Point Conversion.

Fixed-point conversion requires the Fixed-Point Designer™ software.

HDL Coder displays a series of dots to show progress during HDL test bench generation for test benches with a long simulation time.

HDL test bench generation simulates the Simulink model to collect data for every signal in the DUT. This data collection phase can therefore significantly impact HDL test bench generation time. The progress indicator dots help as visual indicators during this long phase of testbench generation.

If you generate a test bench, update the stop time in your model, and regenerate the test bench. The generated test bench uses the updated stop time.

Previously, test bench generation used the original stop time even if the stop time was updated.

In the MATLAB to HDL workflow, HDL Coder uses MEX code for data logging to speed up HDL test bench generation.

When using the IP core generation workflow in the HDL Workflow Advisor, you can program the target SoC device by using an Ethernet connection.

You must have Embedded Coder and the Embedded Coder Support Package for Altera SoC Platform.

Using the CallBackCustomProgrammingMethod method of the hdlcoder.ReferenceDesign class, you can define your own function to program the target device in your custom reference design.

Using the AXI4SlaveInterface method of the hdlcoder.ReferenceDesign class, you can specify the type of an AXI4 slave interface in a custom reference design. The type can be AXI4, or AXI4-Lite. You can also name the interface.

Vision HDL Toolbox introduces a new block, ROI Selector, that selects a region of interest (ROI) from a video stream. You can specify one or more regions by using input ports or mask parameters. The block returns each new region as streaming pixel data and a corresponding pixelcontrol bus.

The visionhdl.ROISelector System object provides equivalent MATLAB functionality.

Vision HDL Toolbox includes new blocks and System objects that perform morphology operations on grayscale input data.

These blocks and System objects support HDL code generation.

The Biquad Filter block is now included in subsystem optimizations for speed and area of the generated HDL. To specify resource sharing, streaming, and pipeline options, right-click the subsystem containing the Biquad Filter block and open the HDL Code > HDL Properties dialog box. To use these optimizations you must set the Architecture of the Biquad Filter block to Fully parallel.

The optimizations work the same way as the optimizations for the Discrete FIR Filter block. You can share resources between Biquad Filter and Discrete FIR Filter blocks in the same subsystem.

You can now choose from three different functions for the Multiply-Add block to map to the DSP blocks in Altera and Xilinx FPGA libraries. The three functions are c+(a.*b), c-(a.*b), and (a.*b)-c.

For details, see Multiply-Add.

If you have Product or Gain blocks with complex input signals in your Simulink model, HDL Coder generates a model with Multiply-Add blocks. These Multiply-Add blocks map efficiently to the DSP blocks in Altera and Xilinx FPGA libraries.

To optimize for area by mapping pipeline registers to RAM, in the Configuration Parameters dialog box, select the Map pipeline delays to RAM check box from the HDL Code Generation > Global Settings > Optimization tab. See MapPipelineDelaysToRAM.

HDL Coder also maps design delays and the pipeline registers in floating-point type to RAM.

If you have delay blocks with in your model with ResetType set to None, HDL Coder generates a script to initialize these delay blocks for simulation with ModelSim.

Previously, you either modified the generated code or wrote your own script to initialize these delay blocks.

In R2016a, to generate one reusable HDL file for Subsystem blocks that contain Gain and Constant blocks for different values of tunable mask parameters, set the MaskParameterAsGeneric option.

Previously, in addition to setting the MaskParameterAsGeneric option, you used Atomic Subsystem blocks and selected the tunable attribute in the Mask Editor Parameters & Dialog tab for the Atomic Subsystem block.

See MaskParameterAsGeneric.

When you enable the Industry coding standard, HDL Coder checks for the length of control flow statements, such as if-else, case and loops, which are described separately within a process block (for VHDL code) or an always block (for Verilog code). If the length of control flow statements in your design exceeds the specified limit, the coder displays an error in the HDL coding standard report.

See HDL Coding Standard Rules.

HDL Coder now supports code generation from MATLAB Function blocks that use the nondirect feedthrough setting. With nondirect feedthrough, you can use MATLAB Function blocks in a feedback loop and prevent algebraic loops.

By default, MATLAB Function blocks have direct feedthrough enabled. To disable it, in the Ports and Data Manager pane, clear the Allow direct feedthrough check box.

Nondirect feedthrough enables semantics to ensure that outputs rely only on current state. For additional information, see Use Nondirect Feedthrough in a MATLAB Function Block.

In R2016a, HDL Coder supports all nested virtual and nonvirtual buses. For example, you can now generate HDL code for a Delay block with a nested virtual bus signal input in your Simulink model.

You can generate HDL code for:

• Stateflow Charts, State Transition Tables, or Truth Tables that use a tunable parameter.

• MATLAB Function blocks that use a tunable or nontunable parameter with vector, array, struct, enumeration, or complex data type.

• MATLAB System blocks containing a System object with tunable properties.

See Generate DUT Ports for Tunable Parameters.

You can generate HDL code for:

• A Bus to Vector block.

• A Dot Product block with Tree architecture when input signals are a mix of row and column vectors.

• A Shift Arithmetic block when Bits to shift: Number is a vector of bit shift values or Bits to shift: Source is Input port.

• Masked Inport and Outport blocks.

• A Matrix Concatenate block with Multidimensional array mode.

• A Bus Assignment block with bus signal input containing a nested bus signal.

• A MATLAB System block containing a user-defined System object with bus inputs or outputs.

• An n-D Lookup Table block with the Breakpoints specification parameter or a Prelookup block with the Specification parameter set to Explicit values or Even spacing.

• A Subsystem block with BlackBox architecture and a cell array variable in the GenericList field as input to the Subsystem block.

HDL Coder has been tested with:

• Xilinx Vivado Design Suite 2015.2

• Altera Quartus II 15.0

For a list of supported, third-party tools and hardware, see Supported Third-Party Tools and Hardware.

For the FPGA Turnkey and Simulink Real-Time FPGA I/O workflows, HDL Coder generates a top-level HDL code wrapper and a constraint file that contains pin mapping and clock constraints. In the HDL Workflow Advisor, for the FPGA Turnkey and Simulink Real-Time FPGA I/O workflows, the name of the Generate RTL Code and Testbench task is now Generate RTL Code.

To run the Annotate Model with Synthesis Result task, your target workflow must be Generic ASIC/FPGA.

Compatibility Considerations

For all workflows, the Generate FPGA top level wrapper check box and GenerateTopLevelWrapper of the hdlcoder.WorkflowConfig class have been removed.

For the Generic ASIC/FPGA workflow, if you specify the GenerateTopLevelWrapper property of the hdlcoder.WorkflowConfig, HDL Coder displays a warning. In a future release, specifying this property will result in an error.

For the FPGA Turnkey or Simulink Real-Time FPGA I/O workflow, if you specify the following hdlcoder.WorkflowConfig properties, HDL Coder displays a warning. In a future release, specifying these properties will result in an error:

• RunTaskGenerateRTLCodeAndTestbench

• RunTaskVerifyWithHDLCosimulation

• RunTaskAnnotateModelWithSynthesisResult

• GenerateRTLTestbench

• GenerateCosimulationModel

• CosimulationModelForUseWith

• GenerateValidationModel

• GenerateTopLevelWrapper

• CriticalPathSource

• CriticalPathNumber

• ShowAllPaths

• ShowDelayData

• ShowUniquePaths

• ShowEndsOnly

If you have non-ASCII content in model annotations and Model Info blocks, HDL Coder issues warnings during checkhdl and makehdl. Non-ASCII characters in the generated HDL code can cause RTL simulation and synthesis tools to fail to compile the code.

For Japanese versions of HDL Coder, the resource utilization report is in Japanese.

For Xilinx Zynq or Altera SoC hardware, you can map tunable parameters in your Simulink model to an AXI4, AXI4-Lite, or external interface in the generated IP core. You can then use the embedded software to dynamically tune the parameter in hardware.

You can also map tunable parameters to the PCI interface in the Simulink Real-Time FPGA I/O workflow.

The HDL Workflow Advisor Target Platform Interface Table shows tunable parameters in the Port Name column. You can map each tunable parameter to a target platform interface as you can with any DUT port.

To make a tunable parameter available for mapping to a target interface, use it in a Gain, Constant, or MATLAB Function block.

You can now generate HDL code for the following blocks with bus input or output signals:

• Enabled Subsystem

• Triggered Subsystem

• Subsystem with black box implementation

The streaming optimization works with:

• Subsystems that contain nested subsystems. Previously, the streamed subsystem had to be a leaf subsystem.

• A streaming factor that is divisible by vector width. Previously, the streaming factor had to be a divisor of the vector width.

• Blocks that are not supported for streaming. Instead, the optimization can work around unsupported blocks. Previously, the presence of unsupported blocks caused streaming to fail.

The resource sharing area optimization can implement shared resources at the clock rate within clock-rate pipelining regions, without using oversampling.

The resource sharing optimization can now share a subset of all the identical atomic subsystems in your design. Previously, you had to share all of the atomic subsystems, or none.

The hierarchy flattening optimization can operate on individual atomic subsystems, even if there are other identical atomic subsystems in the design.

You can generate VHDL^® generic or Verilog^® parameter syntax for model arguments you use in a masked or unmasked Model block. In the model, you can use the model arguments in Gain or Constant blocks.

For details, see Generate Parameterized Code for Referenced Models.

You can use the HDL Workflow Command Line Interface (CLI) to script the entire generic ASIC/FPGA, IP core generation, and FPGA Turnkey workflows.

The simplest way to create the script is to configure your design using the HDL Workflow Advisor, generate a target hardware bitstream or project from your Simulink model, then export a script. You can run the exported script, which contains HDL Workflow CLI commands, to replicate your HDL Workflow Advisor settings and generate the same target hardware bitstream or project.

For details, see Run HDL Workflow with a Script.

You can generate code for subsystems containing Xilinx System Generator for DSP blocks when Xilinx Vivado is your synthesis tool. For setup information, see Xilinx System Generator Setup for ModelSim Simulation.

In the Library Browser, you can enable a filtered view that shows all the blocks that are compatible with HDL code generation. The view shows only those blocks for which you have a license. To use this filtered view, at the command prompt, enter hdllib.

After using the hdllib command, if you close and reopen the Library browser, the view that shows only those blocks that are compatible for HDL code generation persists. To display all blocks in the Library Browser, enter hdllib('off').

For more information, see Show Blocks Supported for HDL Code Generation.

Compatibility Considerations

Previously, the hdllib command created a supported blocks library called hdlsupported. The hdllib command now opens the Library Browser with a view that shows the supported blocks for HDL code generation, but does not create a block library.

To create the supported blocks library, at the command prompt, enter hdllib('librarymodel').

The Configuration Parameters list view shows HDL Code Generation parameters. In list view, you can search, filter, sort, and edit parameters. You can also get command-line parameter names for use in scripts. To use the list view, click the List button at the top of the Configuration Parameters dialog box.

Some of the HDL Code Generation parameters, such as the lint script, synthesis script, and HDL coding standard parameters, are unavailable in list view. To see all the HDL Code Generation parameters, use the category view.

To learn about Configuration Parameters list view, see Configuration Parameters Dialog Box Overview.

You can generate HDL code for a top-level MATLAB design function that has struct inputs or outputs. You can also generate HDL code for a test bench that uses struct data. Previously, struct data was supported within the design, but not at the top-level inputs or outputs.

For example, in Vision HDL Toolbox, this removes the requirement to flatten the pixelcontrol structure into the component signals, as shown here.

function [pixOut,hStartOut,hEndOut,vStartOut,vEndOut,validOut] = ...
                 HDLTargetedDesign(pixIn,hStartIn,hEndIn,vStartIn,vEndIn,validIn)

function [pixOut,ctrlOut] = HDLTargetedDesign(pixIn,ctrlIn)

The structure is flattened to the individual control signals in the generated Verilog or VHDL code.

You can generate code for a Trigonometric Function block with vector inputs when the Function is sin, cos, cos + jsin, or sincos, and the Approximation method is CORDIC.

In the HDL Block Properties dialog box, you can also set UsePipelinedKernel to Off for zero-latency combinatorial HDL code. To avoid delay balancing errors, you can set UsePipelinedKernel to Off if the block is in a feedback loop.

See Trigonometric Function.

When you generate code for a MATLAB Function block that uses a tunable parameter, the coder creates a top-level DUT port for the tunable parameter in the generated code.

For details, see Generate DUT Ports for Tunable Parameters.

HDL code you generate for models that use the configuration parameter Default parameter behavior, which was previously called Inline parameters, follows the new behavior.

To learn more about the Default parameter behavior name and functionality change, see Configuration parameter Inline parameters name and functionality change.

Compatibility Considerations

Sample time propagation for Inf rates in Simulink can differ from previous releases. If you have a model with Inf sample times, check the sample time legend to make sure it shows the rates you expect.

To fix code generation issues from such models, fully specify the sample time. For example, specify the sample time for any Constant blocks with Inf sample time.

You can specify a high-level synthesis objective that maps to your third-party synthesis tool can use to optimize the target hardware. The following high-level synthesis objectives are available from the HDL Workflow Advisor and the HDL Workflow Command Line Interface:

• Area Optimized

• Compile Optimized

• Speed Optimized

• None (default)

For details about how the synthesis objective maps to Tcl commands, see Synthesis Objective to Tcl Command Mapping.

A new block, Multiply-Add, that performs a hardware optimized multiplication-addition operation, is available in the HDL Operations block library. Using this block can help your design map to DSPs in hardware. The resource sharing optimization can also share Multiply-Add blocks.

To learn about the Simulink behavior, see Multiply-Add.

To learn about the hardware implementation and HDL block properties, see Multiply-Add.

For masked subsystems and user library blocks, you can flatten hierarchy to enable further speed and area optimization.

For details, see Hierarchy Flattening.

The loop streaming implementation now uses fewer multiplexers and therefore uses less area.

Register retiming for a complex Gain block inserts a register between the multiplier and adder.

The serializer used in streaming and resource sharing is redesigned as a combinational switch to use less area. It no longer uses registers in its implementation.

The Tapped Delay block is supported for streaming, retiming, and floating-point library mapping. It also no longer inhibits clock-rate pipelining.

In the hardware-software codesign workflow, for streaming applications, you can use vector ports to connect the hardware DUT to the rest of the model. With an Embedded Coder license, you can then generate a software interface model that includes the embedded software DMA driver block for the generated IP core.

In the hardware DUT, connect the top-level input and output vector ports to Serializer1D and Deserializer1D blocks. HDL Coder detects this modeling pattern, and generates a software interface model that replaces the Serializer1D, Deserializer1D, and DUT.

For details, see Model Design for AXI4-Stream Interface Generation.

Using the hdlcoder.ReferenceDesign.addInternalIOInterface method, you can define a connection between your generated IP core and other IP in a custom reference design. You can use this method for Altera Quartus II, Xilinx Vivado, and Xilinx ISE hardware targets.

You can now optimize speed and area of the generated HDL for the Discrete FIR Filter block. Right-click the subsystem containing the Discrete FIR Filter block, and open the HDL Code > HDL Properties dialog to specify resource sharing, streaming, and pipeline options. You can use these optimizations when the Architecture is Fully parallel. This feature requires an HDL Coder license. See Reduce Critical Path with Distributed Pipelining, Resource Sharing of Multipliers to Reduce Area, and HDL Block Properties.

FIR Rate Conversion HDL Optimized block in DSP System Toolbox upsamples, filters, and downsamples a signal using an efficient polyphase FIR structure. The block operates on one sample at a time and provides hardware control signals to pace the flow of samples in and out of the block. The dsp.HDLFIRRateConverter System object provides equivalent MATLAB functionality. Both the block and System object support HDL code generation.

Infrastructure improvements in test bench generation with file I/O have improved test bench performance by reducing:

• Simulation time

• Memory use

• Code generation time

HDL Coder writes the DUT stimulus and reference data from your MATLAB or Simulink simulation to data files (.dat). During HDL simulation, the HDL test bench reads the saved stimulus from the .dat files.

To learn more about Simulink test bench generation, see Test Bench Generation.

To learn more about MATLAB test bench generation, see Test Bench Generation.

Compatibility Considerations

The HDL test bench code generated for a design in a previous release may differ from the code generated for the same design in the current release.

Previously, by default, DUT stimulus and reference data was generated as constants in the test bench code. To generate test bench data that used file I/O, you had to set the UseFileIOInTestBench property to 'on'.

The UseFileIOInTestBench property is now 'on' by default.

In the generic ASIC/FPGA workflow and IP core generation workflow, you can target Xilinx Kintex^® UltraScale and Virtex^® UltraScale devices.

Five examples of image processing and HDL code generation using Vision HDL Toolbox are added in this release.

• Gamma Correction

• Histogram Equalization

• Edge Detection and Image Overlay

• Edge Detection and Image Overlay with Impaired Frame

• Noise Removal and Image Sharpening

If you have a model with a Stateflow Moore Chart, select the Initialize Outputs Every Time Chart Wakes Up chart property. By selecting this property, HDL Coder prevents latching of outputs, generates more readable HDL code, and provides better synthesis results.

Compatibility Considerations

In previous versions, you did not have to set the chart property. Starting in R2015b, If you do not select the Initialize Outputs Every Time Chart Wakes Up check box, HDL Coder generates an error.

For HDL model properties that require ASCII character strings, HDL Coder now generates an error if you assign a non-ASCII string value.

The following model properties accept non-ASCII character strings:

• BlocksWithNoCharacterizationFile

• CriticalPathEstimationFile

• DateComment

• DistributedPipeliningBarriersFile

• HighlightFeedbackLoopsFile

• SimulationLibPath

• SynthesisProjectAdditionalFiles

• TargetDirectory

Compatibility Considerations

Previously, HDL Coder did not generate an error if you assigned a non-ASCII character string to a model property that required ASCII characters.

To fix the error, at the command prompt, enter: hdlset_param (gcs, model_property_name, 'ASCII_value').

You can install and run HDL Coder to generate code on the 64-bit Mac OS X platform.

Critical path estimation helps you to find the timing critical path in your design without running third-party synthesis tools.

If you enable critical path estimation when you generate code, HDL Coder computes the timing critical path and generates a script that highlights the estimated critical path in the generated model.

To find your estimated critical path, in HDL Workflow Advisor > HDL Code Generation > Set Code Generation Options > Set Basic Options, select Generate high-level timing critical path report.

The estimated critical path is calculated using static timing analysis. In the current release, the timing data for each block is based on Xilinx Virtex-7, speed grade -1 hardware.

If a block in your design does not have timing data, the coder generates a second block highlighting script. To see the uncharacterized blocks in your design, click the script link displayed in the MATLAB command window or HDL Workflow Advisor Result pane.

For more information, see Find Estimated Critical Paths Without Synthesis Tools.

You can generate an IP core with an AXI4-Stream interface when you target the Xilinx Zynq-7000 platform and your synthesis tool is Xilinx Vivado.

For an example that shows how to generate an HDL IP core with an AXI4-Stream interface, see Getting Started with AXI4-Stream Interface in Zynq Workflow.

You can now define a custom SoC board or a custom reference design.

In the HDL Workflow Advisor, you can generate an IP core for a custom board, insert it into a custom reference design, and generate an FPGA bit stream for the SoC hardware.

To learn more about defining and registering a custom board or custom reference design, see:

• Board and Reference Design Registration System

• Register a Custom Board

• Register a Custom Reference Design

For an example, see Define and Register Custom Board and Reference Design for SoC Workflow.

You can use pragmas in your MATLAB code to specify pipelining, loop streaming, and loop unrolling optimizations for specific operations.

For a loop statement, you can use coder.hdl.loopspec to specify loop unrolling or loop streaming.

For an operation or expression, you can use coder.hdl.pipeline to insert one or more pipeline registers.

The following example shows how to use these two pragmas:

function y = hdltest(x)
    pv = uint8(1);
    pv = coder.hdl.pipeline(pv + x, 4);
    
    y = uint8(zeros(1,10));
  
    coder.hdl.loopspec('stream', 5);
    for i = 1:10
        y(i) = pv + i;
    end
end

• Pipeline MATLAB Expressions

• Optimize MATLAB Loops

Compatibility Considerations

If you have a model that uses the VariablesToPipeline HDL block property, or a MATLAB design that uses the HDL Workflow Advisor Pipeline variables field, the software displays a warning when you generate code.

Replace instances of Variables ToPipeline or Pipeline variables with coder.hdl.pipeline. VariablesToPipeline and Pipeline variables will be removed in a future release.

Model templates are available for you to use when designing a model for HDL code generation. These model templates show design patterns for using Simulink blocks to model hardware and generate efficient HDL code.

For example, the Simulink Template Gallery contains model templates for ROM, state machines, shift registers, and multipliers that map to DSP48s.

To view the HDL Coder model templates, open the Simulink Library Browser, click the New Model button arrow, and select From Template. In the Simulink Template Gallery, browse to the HDL Coder folder.

For more information, see Simulink Templates For HDL Code Generation.

You can use enumerated data at the top-level DUT ports for your design, whether the DUT is a MATLAB design function, or a Simulink subsystem or model reference.

You can generate a DUT port for tunable parameters that have the following data types:

• Complex

• Vector

• Structure

• Enumeration

You can also generate a DUT port for tunable parameters when your DUT is a model reference.

To learn how to generate code for tunable parameters, see Generate DUT Ports For Tunable Parameters.

You can integrate custom or legacy HDL code into your design with a black box subsystem that contains DocBlock.

In the DocBlock HDL Block Properties dialog box, set Architecture to HDLText and TargetLanguage to your target HDL language. Specify the interface to your custom code by customizing the black box subsystem interface.

For details, see Integrate Custom HDL Code Using DocBlock.

When you enable the Industry coding standard, HDL Coder checks for unknown or high-impedance constants in your design. If your design uses these constants, the coder displays a warning.

For VHDL, the coder checks for X, Z, U, W, H, L, and -. For Verilog, the coder checks for X and Z.

You can generate VHDL code for model references in your design into a single library. To generate code into a single library, set the UseSingleLibrary property to on using makehdl or hdlset_param.

You can map an hdl.RAM System object in your MATLAB code to multiple RAM banks.

If you specify vector inputs to the step method, the hdl.RAM maps to RAM banks. The number of RAM banks is the same as the number of elements in each input vector.

You can generate code for:

• Bus Selector with Output as bus enabled.

• Constant with Output data type set to Bus.

You can specify the timing controller architecture and timing controller postfix in the Configuration Parameters dialog box and HDL Workflow Advisor, from both Simulink and MATLAB.

You can also specify these timing controller options at the command line.

For the Deserializer1D block, you can specify the Initial condition.

Additional Simulink block features are supported for HDL code generation:

• Delay with delay length of 0

• Delay with Show enable port enabled

• Dot Product within a delay balancing region

• Model reference block Description field maps to a comment

• Deserializer1D and Serializer1D support enumeration data.

The generated code has the following coding style improvements:

• Stateflow charts for Moore machines generate code that follows the coding style guidelines from Altera and Xilinx. Open the hdlcoder_fsm_mealy_moore model to see an example of a Moore chart that generates this style of HDL code.

• Comments for a Simulink block appear with the main body of the associated generated code.

• For Unit Delay Resettable, Unit Delay Enabled Resettable, and Delay with External reset set to Level, the reset signal is applied within the clocked region for better synthesis results.

• Fewer temporary variables for improved multiplier mapping and readability.

• Expressions of the form (a+1)-1 are reduced to a.

• One-line boolean expressions are generated when they can replace if-else statements.

• Verilog code generated for arrays of constants is more compact. The number of lines of generated code is reduced by 50%.

You can generate code for the following predefined System objects when you use them in a MATLAB System block:

• hdl.RAM

• comm.HDLCRCDetector

• comm.HDLCRCGenerator

• comm.HDLRSDecoder

• comm.HDLRSEncoder

• dsp.DCBlocker

• dsp.HDLComplexToMagnitudeAngle

• dsp.HDLFFT

• dsp.HDLIFFT

• dsp.HDLNCO

You can partition large multipliers by specifying a maximum multiplier bit width for your design.

To specify the maximum multiplier bit width, in the HDL Workflow Advisor Optimization tab, for Multiplier partitioning threshold, enter an integer value greater than or equal to 2. See also MultiplierPartitioningThreshold.

The following clock-rate pipelining enhancements are available:

• MATLAB Function blocks that do not have state can be pipelined at the clock rate.

• DUT output ports can be pipelined at the clock rate. In the Simulink HDL Workflow Advisor Optimizations tab, enable the Allow clock-rate pipelining of DUT output ports option, or set the ClockRatePipelineOutputPorts property to on.

• HDL Coder generates a MATLAB script that highlights blocks that are inhibiting clock-rate pipelining. You can run the script by clicking the associated link the optimization report.

With distributed pipelining, HDL Coder generates a MATLAB script that highlights blocks that are inhibiting the optimization, and displays messages for highlighted blocks that describe why the block is inhibiting the optimization. The script highlights blocks in your original model and generated model.

To run the highlighting script, click the associated link in optimization report.

Script generation is on by default. You can disable script generation by setting the DistributedPipeliningBarriers property to off with makehdl or hdlset_param.

You can now specify the types of blocks or operations to share in the parts of your design that have resource sharing enabled. You can enable or disable resource sharing for adders, multipliers, atomic subsystems, and MATLAB Function blocks.

You can also specify minimum bit widths for shared adders and multipliers.

You can use speed and area optimizations in designs that contain Unit Delay Enabled, Unit Delay Resettable, and Unit Delay Enabled Resettable blocks. For example, you can use the following optimizations:

• Resource sharing

• Streaming

• Distributed pipelining or retiming

• Input, output, and constrained output pipelining

• Clock-rate pipelining

You can share multipliers or adders when their input ports have the same data types, but in a different order. For example, you can share the following two multipliers:

• Multiplier A, with uint8 data on port X and uint16 data on port Y.

• Multiplier B, with uint16 data on port X and uint8 data on port Y.

When the loop streaming optimization is enabled in MATLAB code, HDL Coder applies the streaming optimization to vector operations to minimize multiplexer and register usage.

The following types of vector operations benefit from vector streaming:

• Single vector operations.

  For example:

  y = u .* v;

• Chained vector operations.

  For example:

  t = u .* v;
  y = t + w;

• Chained vector operations across a persistent variable.

  For example:

  persistent acc;
  if isempty(acc)
      acc = uint16(zeros(size(u)));
  end
  
  t = u .* v;
  acc = t + acc;
  y = acc;

After you achieve your clock frequency target using automatic iterative optimization, you can generate a custom IP core or use the FPGA Turnkey workflow with the optimized design.

When you target the Speedgoat IO331-6 board, in the HDL Workflow Advisor Target platform interface table, you can select TTL I/O Channel [0:15] to connect your design interface to digital I/O pins.

For the IP core generation workflow, when you specify IP core settings, HDL Coder saves the information with your model. The following HDL Workflow Advisor fields are saved with the model as HDL block properties of the DUT block.

For the DUT block, you can set and view IPCoreName, IPCoreVersion, IPCoreAdditionalFiles, and ProcessorFPGASynchronization with the HDL Block Properties dialog box or hdlset_param and hdlget_param. To learn more about the block properties, see Atomic Subsystem or Subsystem

For an example that shows how to configure target hardware settings in your model, see Save Target Hardware Settings in Model.

FIR Decimation and FIR Interpolation blocks now support HDL code generation with data types specified by Inherit via internal rule. These blocks are available in DSP System Toolbox.

For Biquad Filter, FIR Decimation, FIR Interpolation, CIC Decimation, and CIC Interpolation blocks, HDL code generation is supported for Coefficient source set to System object. These blocks and objects are available in DSP System Toolbox.

Find blocks that support HDL code generation, in the ‘DSP System Toolbox HDL Support' and ‘Communications System Toolbox HDL Support' libraries, in the Simulink library browser. Alternately, you can type dsphdllib and commhdllib at the MATLAB command prompt to open these libraries.

The blocks in dsphdllib and commhdllib have their parameters set for HDL code generation.

Vision HDL Toolbox provides pixel-streaming algorithms for the design and implementation of vision systems on FPGAs and ASICs. It provides a design framework that supports a diverse set of interface types, frame sizes, and frame rates, including high-definition (1080p) video. The image processing, video, and computer vision algorithms in the toolbox use an architecture appropriate for HDL implementations.

The toolbox algorithms are designed to generate readable, synthesizable code in VHDL and Verilog (with HDL Coder). The generated HDL code can process 1080p60 in real time.

Toolbox capabilities are available as MATLAB System objects and Simulink blocks.

See Vision HDL Toolbox

The Verification of HDL Implementation of LTE OFDM Modulator and Detector example uses Simulink blocks that support HDL code generation to implement a hardware-friendly LTE Orthogonal Frequency Division Multiplexing (OFDM) modulator and detector. Running this example requires LTE System Toolbox™.

HDL Coder has been tested with:

• Xilinx Vivado Design Suite 2014.2

• Altera Quartus II 14.0

For a list of supported third-party tools and hardware, see Supported Third-Party Tools and Hardware.

In the Simulink to HDL workflow, for speed optimizations that insert pipeline registers, the coder identifies multi-cycle paths in your design and inserts pipeline registers at the clock rate instead of the data rate. When the optimization is in a slow-rate region or multi-cycle path of the design, clock rate pipelining enables the software to perform optimizations without adding extra latency, or by adding minimal latency. It also enables optimizations such as pipelining and floating-point library mapping inside feedback loops.

Clock-rate pipelining is enabled by default. You can disable clock-rate pipelining in one of the following ways:

• In the HDL Workflow Advisor, in the HDL Code Generation > Set Code Generation Options > Set Advanced Options > Optimization tab, select Clock-rate pipelining.

• At the command line, use makehdl or hdlset_param to set the ClockRatePipelining parameter to off.

For details, see Clock-Rate Pipelining.

The HDL Coder software is now tested with Xilinx Vivado Design Suite 2013.4. You can:

• Generate a custom IP core for the Zynq-7000 platform and automatically integrate it into a Vivado project for use with IP Integrator.

• Program FPGA hardware supported by Vivado using the HDL Workflow Advisor.

• Perform back-annotation analysis of your design.

• Generate synthesis scripts.

You can generate a custom IP core with an AXI4 interface for the Altera SoC platform.

HDL Coder can also insert your custom IP core into a predefined Qsys project to target the Altera Cyclone V SoC development kit or Arrow SoCKit development board. The coder can connect the IP core to the ARM processor via the AXI interface within the project.

The software provides add-on support for Altera SoC hardware via the HDL Coder Support Package for Altera SoC Platform. For more details, see HDL Coder Support Package for Altera SoC Platform.

You can use a black box System object, hdl.BlackBox, to integrate custom HDL code into your design in the MATLAB to HDL workflow. For example, you can integrate handwritten or legacy HDL code that you previously generated from MATLAB code or a Simulink model.

For an example that shows how to use hdl.BlackBox, see Integrate Custom HDL Code Into MATLAB Design.

You can integrate custom HDL code, such as handwritten or legacy HDL code, into your design in the MATLAB to HDL IP core generation workflow. Use one or more hdl.BlackBox System objects in your MATLAB design, and add the HDL source files in the Additional source files field.

To learn how to use the Additional source files field, Generate a Board-Independent IP Core from MATLAB.

You can directly generate code for a model reference, without placing it in a Subsystem block. Previously, the code generation DUT had to be a Subsystem block.

You can generate code for the dsp.HDLFFT and dsp.HDLIFFT System objects, Complex to Magnitude-Angle HDL Optimized block, and dsp.ComplexToMagnitudeAngle System object, which are available in the DSP System Toolbox.

For details of the updates to the FFT HDL Optimized and IFFT HDL Optimized blocks, see the DSP System Toolbox release notes.

Compatibility Considerations

The FFT HDL Optimized and IFFT HDL Optimized blocks take fewer cycles to compute one frame of output than in previous releases. For instance, for the default 1024-point FFT, the latency in R2014a was 1589 cycles whereas in R2014b the latency is 1148. The latency is displayed on the block icon.

If you have manually matched latency paths in models using the R2014a version of the FFT HDL Optimized and IFFT HDL Optimized block, adjust the delay on those paths to accommodate the lower FFT latency.

The coder generates a top-level DUT port for each tunable parameter in your DUT that you use as the Gain parameter in a Gain block, or the Constant value parameter in a Constant block.

For details, see Generate Code For Tunable Parameters.

If you enable active state output to show child activity or leaf state activity for a Stateflow block, the coder generates code for the active state output. See Active State Output.

If you enable HDL coding standard rule checking, you can enable or disable specific rules. You can specify rule parameters. For example, you can specify the maximum nesting depth for if-else statements. See HDL Coding Standard Customization.

You can now generate a lint tool script for Mentor Graphics^® HDL Designer.

To learn about HDL lint script generation for your Simulink design, see Generate an HDL Lint Tool Script.

To learn about HDL lint script generation for your MATLAB design, see Generate an HDL Lint Tool Script.

You can minimize clock enable logic in your generated code by setting the MinimizeClockEnables property of the coder.HdlConfig object to true, or by enabling the Minimize clock enables option in the HDL Workflow Advisor.

For details, see Minimize Clock Enables.

For each block supported for code generation, the HDL Block Properties dialog box Architecture drop-down list shows only the architectures that are valid for the block based on mask parameter settings. Previously, all architectures were available for selection regardless of mask parameter settings, and invalid settings caused errors during code generation.

The HDL Reciprocal block is available with Simulink. Use this block to implement division operations in models intended for HDL code generation. HDL Reciprocal has two Newton-Raphson HDL implementations, ReciprocalNewton and ReciprocalNewtonSingleRate. The new implementations use fewer hardware resources and can achieve higher clock frequency than Divide or Math Function HDL block implementations.

For the Divide and Math Function blocks, the names of the Newton-Raphson HDL block implementations have changed:

• RecipNewton is now ReciprocalRsqrtBasedNewton.

• RecipNewtonSingleRate is now ReciprocalRsqrtBasedNewtonSingleRate.

If you open a model from a previous release, HDL Coder automatically maps the RecipNewton and RecipNewtonSingleRate implementation names to ReciprocalRsqrtBasedNewton and ReciprocalRsqrtBasedNewtonSingleRate, respectively.

To learn about the HDL Reciprocal block, see HDL Reciprocal.

To learn about the ReciprocalNewton and ReciprocalNewtonSingleRate implementations, see HDL Reciprocal.

The following new blocks are available from the HDL Operations library for simulation and code generation:

• Serializer1D

• Deserializer1D

The following blocks are now supported for code generation:

• Backlash

• Bus assignment

• Coulomb and Viscous Friction

• DC Blocker

• Dead Zone/Dead Zone Dynamic

• Discrete PID Controller

• Hit Crossing

• HDL Reciprocal

• Serializer1D/Deserializer1D

• Wrap to Zero

When you generate code for a RAM block from the HDL Operations library, the name in the generated code reflects the name in the model. Similarly, port signal names in the generated code are inherited from your model.

For each RAM block of a particular size, the coder generates an HDL module. The module file name reflects the name and size of the RAM block or persistent variable in your design.

For example, suppose DPRAM_foo is the name of a Dual Port RAM block in your model. The generated code for the instance is:

u_DPRAM_foo : DualPortRAM_Wrapper_256x8b

DualPortRAM_256x8b.vhd
DualPortRAM_Wrapper_256x8b.vhd

When you generate VHDL code for block architectures that use replicated structures, the coder generates for-generate statements for better readability. For example, VHDL code generated for the Add and Product blocks uses for-generate statements.

You can generate code for user-defined System objects that contain child user-defined System objects.

You can generate code for the output and update methods in user-defined System objects that inherit from the matlab.system.mixin.Nondirect class.

Private properties in user-defined System objects can map to RAM. For details, see Implement RAM Using a Persistent Array or System object Properties.

The hdlram System object has been renamed to hdl.RAM and is now available with MATLAB. Previously, hdlram required a Fixed-Point Designer license.

Compatibility Considerations

If you open a design that uses hdlram, the software displays a warning. For continued compatibility with future releases, replace instances of hdlram with hdl.RAM.

For the IP core generation workflow, FPGA turnkey workflow, or Simulink Real-Time FPGA I/O workflow, when you map each of your DUT top-level ports to a platform interface, HDL Coder saves the interface mapping information as port properties in your model. The coder also saves workflow and target platform information with the model.

For DUT Inport and Outport blocks, you can set and view IOInterface and IOInterfaceMapping with the HDL Block Properties dialog box or hdlset_param and hdlget_param.

For an example that shows how to configure target platform interface settings, see http://www.mathworks.com/help/releases/R2014b/hdlcoder/examples/save-target-hardware-settings-in-model.html.

You can generate a MATLAB script that highlights feedback loops that may inhibit delay balancing or speed and area optimizations. The script highlights feedback loops in your original model and generated model.

You can also save the highlighting information in a MATLAB script.

For details, see Find Feedback Loops.

The following optimizations are now supported for enabled subsystems and triggered subsystems:

• Resource sharing

• Streaming

• Constrained overclocking

• Floating-point library mapping

• Hierarchy flattening

• Delay balancing

• Automatic iterative optimization

HDL code generation now supports variable pipelining inside conditional MATLAB code for the MATLAB to HDL workflow and the MATLAB Function block in the Simulink to HDL workflow.

When you have matrices in your MATLAB code, you can generate 2-D matrices in HDL code. By default, the software generates HDL vectors with additional index computation logic, which can use more area in the synthesized hardware than HDL matrices.

To generate 2-D matrix types in HDL in the MATLAB to HDL workflow:

• In the HDL Workflow Advisor, in the HDL Code Generation > Coding Style tab, select Use matrix types in HDL code.

• At the command line, set the UseMatrixTypesInHDL property of the coder.HdlConfig object to true.

Previously, 2-D matrix types could be generated in HDL for the Simulink MATLAB Function block, but not in the MATLAB to HDL workflow.

When you enable 2-D matrix types in the generated HDL code, for the MATLAB to HDL workflow and Simulink to HDL workflow, speed and area optimizations are available. Previously, for the MATLAB Function block, the UseMatrixTypesInHDL parameter was incompatible with speed and area optimizations.

When you enable the Generate validation model option, HDL Coder generates the validation model even if delay balancing is unsuccessful. In previous releases, if delay balancing was unsuccessful, the coder did not generate the validation model.

Starting in R2014b, each hardware support package that you install comes with its own documentation. For a list of support packages available for HDL Coder, with links to documentation, see HDL Coder Supported Hardware.

You can generate code for Simulink, MATLAB, or Stateflow enumerations within your design. In the current release, you cannot generate code if your design uses enumerations at the top-level DUT ports.

To learn more about code generation support for enumerations in Simulink designs, see Enumerations.

To learn more about code generation support for enumerations in MATLAB designs, see Data Types and Scope.

You can target the Xilinx Zynq-7000 AP ZC706 Evaluation Board for IP core generation and Xilinx EDK project integration. After you install the HDL Coder Support Package for Xilinx Zynq-7000 Platform, ZC706 hardware support is available.

You can use the hdlcoder.optimizeDesign function to achieve either your target clock frequency or a maximum clock frequency. Based on your clock frequency goal and target device, the software iteratively generates and synthesizes code, retrieves back annotation data, and inserts delays into your Simulink model to break the critical path.

To learn more, see Automatic Iterative Optimization.

You can generate code for the FFT HDL Optimized and IFFT HDL Optimized blocks, which are available in the DSP System Toolbox.

The HDL Coder library, which contains blocks supported for HDL code generation, is available in Simulink. When you create a model using the HDL Coder library, the blocks are preconfigured with settings suitable for code generation.

The HDL Operations library, previously called hdldemolib, is available in Simulink as part of the HDL Coder library. Previously, the HDL Operations blocks were available only with an HDL Coder license.

To view the HDL Operations block library from the Simulink Library Browser, open the HDL Coder folder and select HDL Operations.

You can generate code for designs that contain:

• DUT ports connected to buses.

• Buses that are not defined with a bus object.

• Nonvirtual buses.

To learn more, see Buses.

You can generate code for designs containing Variant Subsystem blocks. Using Variant Subsystem blocks enables you to explore and generate code for different component implementations and design configurations.

You can generate code that uses the trigger signals in Triggered Subsystem blocks as clocks. Using triggers as clocks enables you to partition your design into different clock regions in the generated code, but can cause a timing mismatch during testbench simulation.

For details, see Use Trigger As Clock in Triggered Subsystems.

You can now generate 2-D matrices in HDL code when you have MATLAB matrices in a MATLAB Function block. By default, the software generates HDL vectors with additional index computation logic, which can use more area in the synthesized hardware than HDL matrices.

For details, see UseMatrixTypesInHDL.

You can generate code for uint64 and int64 data types in MATLAB code, both in the MATLAB-to-HDL workflow and for the MATLAB Function block in the Simulink-to-HDL workflow.

MATLAB Function block ports must use sfix64 or ufix64 types for 64-bit data, because uint64 and int64 are not yet supported in Simulink.

The MATLAB System block, which you use to include System objects in Simulink models, now supports HDL code generation.

For details, see MATLAB System.

HDL code generation now supports System object step method calls inside conditional code regions.

If your MATLAB code includes a System object that does not have states, you do not need to include the persistent keyword for HDL code generation.

For details, see Limitations of HDL Code Generation for System Objects.

A new block, Dual Rate Dual Port RAM, is available for simulation and code generation.

The Dual Rate Dual RAM supports two simultaneous read or write accesses at two Simulink rates. When you generate code, the Dual Rate Dual Port RAM block infers a dual-clock dual-port RAM in most FPGAs.

To view the block, open the HDL Operations block library.

For more information about the block, see Dual Rate Dual Port RAM. For HDL code generation details, see Dual Rate Dual Port RAM.

You can clock your design on the falling edge of the clock.

To generate code that clocks your design on the negative edge of the clock, in the Configuration Parameters dialog box, for HDL Code Generation > Global Settings > Clock Edge, select Falling edge.

Alternatively, at the command line, set the ClockEdge property to 'Falling' using makehdl or hdlset_param.

For details, see ClockEdge.

You can specify bidirectional ports for Subsystem blocks that have Architecture set to BlackBox. In the FPGA Turnkey workflow, you can use the bidirectional ports to connect to external RAM.

In the generated code, the ports have the Verilog or VHDL inout keyword. However, Simulink does not support bidirectional ports, so you cannot simulate the bidirectional behavior in Simulink.

To learn more, see Specify Bidirectional Ports.

You can use the Icon display block parameter on Inport and Outport blocks to make your code more readable. When you set the Icon display parameter to Signal name, Port number, or Port number and signal name, the port names in the generated code match the display names of the connected signals.

The following blocks and block implementations are now supported for code generation:

• Sine, Cosine

• Enumerated Constant

• Delay with External reset set to Level.

  

• Multiport Switch with enumerated type at control input.

  You can set Data port order to Specify indices, and enter enumeration values for the Data port indices. For example, you can connect the Enumerated Constant block to the Multiport Switch control port and use the enumerated types as data port indices.

  

The HDL FIFO block no longer requires a DSP System Toolbox license. The HDL FIFO block is available in the HDL Operations library.

If your design contains blocks or block architectures that are not supported for HDL code generation, the software shows an error and does not generate code. Previously, the software showed a warning, but still generated code, with black box interfaces for the unsupported blocks or block architectures.

Compatibility Considerations

If you want to generate code for models containing unsupported blocks or block architectures, you must Comment out the unsupported blocks in Simulink.

The Model block default architecture is ModelReference. Previously, the default architecture was BlackBox.

Compatibility Considerations

When you open a model created in a previous release, a Model block in that design changes architecture from BlackBox to ModelReference if all the HDL block properties are set to default settings.

To keep the BlackBox architecture for Model blocks, use one of the following workarounds:

• Open the model using the current release, specify the BlackBox architecture for the affected Model blocks, and save the model.

• Open the model using a previous release, specify a nondefault setting for each Model block, and save the model.

The coder does not generate a top-level reset port when the code generation subsystem does not contain resettable delays or blocks.

To generate code without a top-level reset port:

• Set the ResetType HDL block parameter to none for all blocks in the DUT with the ResetType parameter.

• For MATLAB Function blocks in your DUT, do not enable block level HDL optimizations, which insert resettable registers.

For details, see ResetType.

You can generate a reset port for the timing controller, which generates the clock, clock enable, and reset signals in a multirate DUT.

To generate a reset port for the timing controller, set the TimingControllerArch property to resettable using makehdl or hdlset_param.

To learn more, see Generate Reset for Timing Controller.

You can now generate code that includes synthesis attributes to specify multipliers in your design that you want to map to DSPs or logic in hardware. If you specify resource sharing, the software does not share multipliers that have different synthesis attribute settings.

For Xilinx targets, the generated code uses the use_dsp48 attribute. For Altera targets, the generated code uses the multstyle attribute.

For details, see DSPStyle.

You can now generate a lint tool script for Real Intent Ascent Lint.

To learn about HDL lint script generation for your Simulink design, see Generate an HDL Lint Tool Script.

To learn about HDL lint script generation for your MATLAB design, see Generate an HDL Lint Tool Script.

The RAM mapping scheduling algorithm now minimizes overclocking when your MATLAB code maps to multiple RAMs. In addition, multiple persistent variables with cyclic read-write dependencies can now map to RAM.

In the Simulink-to-HDL workflow, and hardware-software codesign workflow, HDL Coder does not rerun code generation or synthesis tasks unless you have changed your model or other hardware-related project settings. You can save time when you want to regenerate HDL code or FPGA programming files without changing your model, code generation options, or hardware target.

Similarly, in the hardware and software codesign workflow, when you modify the embedded software part of your design without changing the hardware part, HDL Coder does not rerun HDL code generation or synthesis tasks.

When the coder skips code generation or synthesis tasks, the HDL Workflow Advisor shows a message. The message contains a link you can click to force the coder to rerun the task.

You can integrate custom HDL code into your design in the Simulink-to-HDL IP core generation workflow. You can integrate handwritten or legacy HDL code into an IP core that you generate from a Simulink model.

To include custom HDL code in your IP core design, use one or more Model or Subsystem blocks with Architecture set to BlackBox. Use the Additional source files field in the HDL Workflow Advisor to specify corresponding HDL file names.

For details of the IP core generation workflow, see Generate a Custom IP Core from Simulink.

When you enable distributed pipelining, you can specify a priority for Distributed pipelining priority: Numerical integrity, or Performance. In the previous release, the distributed pipelining algorithm prioritized numerical integrity.

For details, see DistributedPipeliningPriority.

You can use the Preserve design delays option to prevent distributed pipelining from moving design delays in your Simulink or MATLAB design. If you specify Preserve design delays, distributed pipelining does not move the following design delays:

• Persistent variable in MATLAB code, a MATLAB Function block, or a Stateflow Chart

• Unit Delay block

• Integer Delay block

• Memory block

• Delay block from DSP System Toolbox

• dsp.Delay System object from DSP System Toolbox

For details, see PreserveDesignDelays.

With the resource sharing area optimization, the software shares the maximum number of shareable resources within your overclocking constraints, even if the sharing factor that you specify is not an integer divisor of the number of shareable resources. This capability can increase resource sharing, and therefore reduce area.

For example, if your subsystem has 11 multipliers, and you set SharingFactor to 4, the coder can implement your design with 3 multipliers: 2 multipliers shared 4 ways, and 1 multiplier shared 3 ways. In the previous release, the coder implemented the design with 5 multipliers: 2 multipliers shared 4 ways, and 3 unshared multipliers. The resulting implementation requires overclocking by a factor of 4.

To learn more, see Resource Sharing For Area Optimization.

When the coder balances delays in a multirate model, it now inserts a single delay at the transition from a much faster rate to a slow rate, and passes through the data samples aligned with the slow rate. Previously, the coder inserted a large number of delays at the faster rate.

The coder removes back-to-back serializer-deserializer and multiplexer-demultiplexer pairs introduced by the implementation of optimizations such as resource sharing and streaming. This results in more area-efficient HDL code.

In the Simulink-to-HDL workflow, you can set up and add a synthesis tool without having to close and reopen the HDL Workflow Advisor. In the HDL Workflow Advisor, in the Set Target > Set Target Device and Synthesis Tool task, click Refresh to detect and add the new tool.

You can also set up and add a simulation tool after creating a MATLAB-to-HDL project without having to close and reopen the project. In the HDL Workflow Advisor, in the HDL Verification > Verify with HDL Test Bench task, click Refresh list to detect and add the new tool.

In earlier releases, to set up a compiler to accelerate test bench simulation for MATLAB algorithms, you were required to run mex -setup. Now, the code generation software automatically locates and uses a supported installed compiler. You can use mex -setup to change the default compiler. See Changing Default Compiler.

The xPC Target FPGA I/O workflow is now called the Simulink Real-Time FPGA I/O workflow. This change reflects the xPC Target™ product name change to Simulink Real-Time. For details about the product name change, see New product that combines the functionality of xPC Target and xPC Target Embedded Option.

HDL Coder has been tested with:

• Xilinx ISE 14.6

• Altera Quartus II 13.0 SP1

For a list of supported third-party tools and hardware, see Supported Third-Party Tools and Hardware.

You cannot save a model that uses an attached control file to apply HDL model or block parameters.

Since the R2010a release, if you open a model that uses a control file, the software shows a warning, and updates the model by applying the HDL parameters to your model and removing the control file. For continued compatibility with future releases, save the updated model.

You can generate HDL code from referenced models using the Model block. To use a referenced model in a subsystem intended for code generation, in the HDL Block Properties dialog box, set Architecture to ModelReference.

The coder incrementally generates code for referenced models according to the Configuration Parameters dialog box > Model Referencing pane > Rebuild options. However, the coder treats If any changes detected and If any changes in known dependencies detected as the same. For example, if you set Rebuild to either If any changes detected or If any changes in known dependencies detected, the coder regenerates code for referenced models only when the referenced models have changed.

To learn more, see Model Referencing for HDL Code Generation.

You can now generate HDL code from user-defined System objects written in MATLAB. System objects enable you to create reusable HDL IP.

The step method specifies the HDL implementation behavior. It is the only System object method supported for HDL code generation.

User-defined System objects are not supported for automatic fixed-point conversion.

To learn how to define a custom System object, see Generate Code for User-Defined System Objects.

The coder now infers RAM from persistent array variables accessed within conditional statements, such as if-else or switch-case statements, for both MATLAB designs and MATLAB Function blocks in Simulink.

If you have nested conditional statements, the persistent array variables can map to RAM if accessed in the topmost conditional statement, but cannot map to RAM if accessed in a lower level nested conditional statement.

You can now generate HDL code for subsystems that include blocks from the Altera DSP Builder Advanced Blockset.

For details, see Create an Altera DSP Builder Subsystem.

To see an example that shows HDL code generation for an Altera DSP Builder subsystem, see Using Altera DSP Builder Advanced Blockset with HDL Coder.

When you generate an IP core from your MATLAB design or Simulink model, HDL Coder can automatically insert the IP core into a predefined Xilinx ZC702 or ZedBoard™ EDK project for the Zynq-7000 platform. The coder automatically connects the IP core to the AXI interface and ARM processor in the EDK project.

For an overview of the hardware and software codesign workflow, see Hardware and Software Codesign Workflow.

For an example that shows how to deploy your MATLAB design in hardware and software on the Zynq-7000 platform, see Getting Started with HW/SW Co-design Workflow for Xilinx Zynq Platform.

For an example that shows how to deploy your Simulink model in hardware and software on the Zynq-7000 platform, see Getting Started with HW/SW Co-design Workflow for Xilinx Zynq Platform.

You can now generate a custom IP core with an AXI4-Lite or AXI4-Stream Video interface from a MATLAB design. You can integrate the generated IP core into a larger design in your Xilinx EDK project.

You can also automatically program an Altera or Xilinx FPGA development board with code generated from your MATLAB design, using the HDL Workflow Advisor FPGA Turnkey workflow. To learn how to use this workflow, see Program Standalone FPGA with FPGA Turnkey Workflow and mlhdlc_tutorial_turnkey_led_blinking.

Previously, IP core generation and FPGA Turnkey were available only for the Simulink to HDL workflow.

You can now generate instantiable Verilog modules or VHDL entities when you generate code for local functions in a MATLAB Function block, or for functions on your path that are called from within a MATLAB Function block.

To enable this feature, in the HDL Block Properties dialog box, set InstantiateFunctions to on. For details, see InstantiateFunctions.

MATLAB Function blocks and Stateflow charts with bus signal inputs or outputs are now supported for code generation. The bus must be defined with a bus object.

The coder now automatically inserts a no-reset register at the output of a constant matrix access. Many synthesis tools infer a ROM from this code pattern. For details, see Map Matrices to ROM.

The coder no longer generates a top level reset port when the ResetType HDL block parameter is set to none for all RAM blocks in the DUT.

In previous releases, the generated code included a reset port even when the RAM reset logic was suppressed.

The coder now places a pipeline register between an adder or multiplier and associated rounding or saturation logic when distributing pipelining registers. This register placement can significantly improve clock frequency.

The coder now follows these industry standard coding style guidelines when generating HDL code:

• Division by a power of 2 becomes a bit shift operation.

• Constants with double data types in the original design are automatically converted to their canonical fixed-point types as long as there is no loss of precision.

• SystemVerilog keywords are treated as reserved words.

• Intermediate signals and latches are reduced when HDLCodingStandard is set to Industry.

• Real data types generate warnings, except when you target an FPGA floating-point library.

HDL Coder now generates the coding standard report according to target language. Coding standard errors, warnings, and messages that do not pertain to your target language no longer appear in the report.

The coding standard report is generated in text file format, in addition to HTML format, to enable easier comparison between multiple runs.

HDL Coder now generates code for the coder.load function, which you can use to load compile-time constants from a MAT-file. You no longer have to manually type in constants that were stored in a MAT-file.

To learn how to use coder.load for HDL code generation, see Load constants from a MAT-File.

You can now use the UI to generate Atrenta SpyGlass, Synopsys^® Leda, or custom lint scripts in the Simulink-to-HDL and MATLAB-to-HDL workflows.

To learn about HDL lint script generation for your Simulink design, see Generate an HDL Lint Tool Script.

To learn about HDL lint script generation for your MATLAB design, see Generate an HDL Lint Tool Script.

You can now set up and add a synthesis tool after creating a MATLAB-to-HDL project without having to close and reopen the project. In the HDL Workflow Advisor, in the Set Code Generation Target task, click Refresh list to detect and add the new tool. For details, see Add Synthesis Tool for Current MATLAB Session.

You can now generate a Microsemi Libero or custom synthesis tool script during Simulink-to-HDL and MATLAB-to-HDL code generation.

In the MATLAB-to-HDL workflow, you can now generate synthesis tool scripts customized for Xilinx ISE, Microsemi Libero, Mentor Graphics Precision, Altera Quartus II, and Synopsys Synplify Pro^®. The coder populates the scripts with default options, but you can further customize the scripts as needed. In previous releases, you had to enter the synthesis tool commands manually. For details, see Generate Synthesis Scripts.

You can now specify the generated VHDL or Verilog test bench to use file I/O to read input stimulus and output response data during simulation, instead of including data constants in the test bench code. Doing so improves scalability for designs requiring long simulations and large test vectors.

This feature is available for Simulink-to-HDL and MATLAB-to-HDL code generation.

To learn about test bench generation with file I/O in the Simulink-to-HDL workflow, see Generate Test Bench With File I/O.

To learn about test bench generation with file I/O in the MATLAB-to-HDL workflow, see Generate Test Bench With File I/O.

When you enable FPGA target-specific floating-point library mapping, you can now generate code from a design containing both floating-point and fixed-point components. The coder determines whether to map to a floating-point IP block based on the data types in your model.

The HDL Workflow Advisor target workflow that programs Speedgoat boards to run with xPC Target is now called the xPC Target FPGA I/O workflow. This workflow is separate from the FPGA Turnkey workflow for Altera and Xilinx FPGA boards.

For an example that shows how to use the xPC Target FPGA I/O workflow, see Generate Simulink Real-Time Interface for Speedgoat Boards.

The AXM-A75 AD/DA module for Speedgoat IO331 FPGA board is now available as a hardware target for the xPC Target FPGA I/O workflow.

The xPC Target FPGA I/O workflow now supports the Speedgoat IO321 board and its variant, Speedgoat IO321-5, as separate hardware targets. Previously, the name of the IO321-5 board was IO325.

To learn more about the IO321 and IO321-5 boards, see Speedgoat IO321.

When you enable distributed pipelining for a MATLAB Function block without persistent variables, set the Loop Optimization option to Unrolling for better timing results.

You can now specify a start value for the HDL Counter block. When the counter initializes or wraps around, it counts from the specified start value.

For the Single Port RAM block, Simple Dual Port RAM block, Dual Port RAM block, and hdlram System object, the maximum address width is now 32 bits. For more information, see:

• hdlram

• RAM Blocks

HDL support for the NCO block will be removed in a future release. Use the NCO HDL Optimized block instead.

Compatibility Considerations

In the current release, if you generate HDL code for the NCO block, a warning message appears. In a future release, any attempt to generate HDL code for the NCO block will cause an error.

The suffix for generated fixed-point files is now _fixpt. Previously, the suffix was _FixPt.

Compatibility Considerations

If you have MATLAB-to-HDL projects from previous releases that depend on the generated fixed-point file name, you can use the FixPtFileNameSuffix property to set the suffix to _FixPt.

Generate a custom IP core for the ZC702 or ZedBoard on the Xilinx Zynq-7000 platform using the IP core generation workflow.

To install this support package for MATLAB-to-HDL code generation:

1. In the HDL Workflow Advisor, in the Select Code Generation Target task, set Workflow to IP Core Generation.

2. For Platform, select Get more.

3. Use Support Package Installer to install the HDL Coder Support Package for Xilinx Zynq-7000 Platform.

To install this support package for Simulink-to-HDL code generation:

1. In the HDL Workflow Advisor, in the Set Target > Set Target Device and Synthesis Tool task, set Target workflow to IP Core Generation.

2. For Target platform, select Get more.

3. Use Support Package Installer to install the HDL Coder Support Package for Xilinx Zynq-7000 Platform.

Program Altera FPGA boards with your generated HDL code using the FPGA Turnkey workflow.

To install this support package for MATLAB-to-HDL code generation:

1. In the HDL Workflow Advisor, in the Select Code Generation Target task, set Workflow to FPGA Turnkey.

2. For Platform, select Get more boards.

3. Use Support Package Installer to install the HDL Coder Support Package for Altera FPGA Boards.

To install this support package for Simulink-to-HDL code generation:

1. In the HDL Workflow Advisor, in the Set Target > Set Target Device and Synthesis Tool task, set Target workflow to FPGA Turnkey.

2. For Target platform, select Get more boards.

3. Use Support Package Installer to install the HDL Coder Support Package for Altera FPGA Boards.

Compatibility Considerations

Previous versions of HDL Coder had built-in support for Altera FPGA boards in the FPGA Turnkey workflow. The current version of HDL Coder does not have built-in support for Altera FPGA boards. To get support for Altera FPGA boards, install the HDL Coder Support Package for Altera FPGA Boards.

Program Xilinx FPGA boards with your generated HDL code using the FPGA Turnkey workflow.

To install this support package for MATLAB-to-HDL code generation:

1. In the HDL Workflow Advisor, in the Select Code Generation Target task, set Workflow to FPGA Turnkey.

2. For Platform, select Get more boards.

3. Use Support Package Installer to install the HDL Coder Support Package for Xilinx FPGA Boards.

To install this support package for Simulink-to-HDL code generation:

1. In the HDL Workflow Advisor, in the Set Target > Set Target Device and Synthesis Tool task, set Target workflow to FPGA Turnkey.

2. For Target platform, select Get more boards.

3. Use Support Package Installer to install the HDL Coder Support Package for Xilinx FPGA Boards.

Compatibility Considerations

Previous versions of HDL Coder had built-in support for Xilinx FPGA boards in the FPGA Turnkey workflow. The current version of HDL Coder does not have built-in support for Xilinx FPGA boards. To get support for Xilinx FPGA boards, install the HDL Coder Support Package for Xilinx FPGA Boards.

With the R2013b release, HDL Coder HDL workflow advisor for Simulink supports double and single data types on the DUT interface for test bench generation using HDL Verifier.

Several FPGA boards have been added to the HDL Verifier FPGA board support packages, including Xilinx KC705 and Altera DSP Development Kit, Stratix V edition. You can select these boards for FIL verification using the HDL workflow advisor for Simulink.

The coder can now use static range analysis to derive fixed-point data types for your floating-point MATLAB code.

The redesigned interface for floating-point to fixed-point conversion enables you to use simulation with multiple test benches, static range analysis, or both, to determine fixed-point data types for your MATLAB variables.

For details, see Automated Fixed-Point Conversion.

You can now specify pipeline register insertion for variables in your MATLAB code. This feature is available in both the MATLAB to HDL workflow and the MATLAB Function block.

To learn how to pipeline variables in the MATLAB to HDL workflow, see Pipeline MATLAB Variables.

To learn how to pipeline variables in the MATLAB Function block, see Pipeline Variables in the MATLAB Function Block.

You can now constrain the resource sharing and streaming optimizations to prevent or reduce overclocking. The coder optimizes your design based on two parameters that you specify: maximum oversampling ratio, MaxOversampling, and maximum computation latency, MaxComputationLatency.

For single-rate resource sharing or streaming, you can set MaxOversampling to 1.

To learn more about constrained overclocking, maximum oversampling ratio, and maximum computation latency, see:

• Optimization With Constrained Overclocking

• Maximum Oversampling Ratio

• Maximum Computation Latency

You can now generate custom IP cores with an AXI4-Lite or AXI4-Stream Video interface. You can integrate these custom IP cores with your design in a Xilinx EDK environment for the Xilinx Zynq-7000 Platform.

For more details, see Custom IP Core Generation.

To view an example that shows how to generate a custom IP core, at the command line, enter:

hdlcoder_ip_core_led_blinking

The coder can now automatically synchronize communication and data transfers between your processor and FPGA. You can use the new Processor/FPGA synchronization mode in the FPGA Turnkey workflow with xPC Target, or when you generate a custom IP core.

For more details, see Processor and FPGA Synchronization.

You can now generate code from a MATLAB Function block containing System objects.

For details, see System Objects under MATLAB Language Support, in MATLAB Function Block Usage.

You can now specify a resource sharing factor for the MATLAB Function block to share multipliers in the MATLAB code.

For details, see Resource Sharing and Specify Resource Sharing.

You can now disable delay balancing for a subsystem within your DUT subsystem.

For details, see Balance Delays.

You can now share multipliers used in a single complex multiplication in the Product block. Distributed pipelining can also move registers between the multiply and add stages of a complex multiplication.

You can now use the Speedgoat IO331 Spartan-6 FPGA board in the FPGA Turnkey workflow with xPC Target.

You must have an xPC Target license to use this feature.

With the MATLAB HDL Workflow Advisor, the HDL Verification step includes automation for the following workflows:

• Verify with HDL Test Bench: Create a standalone test bench. You can choose to simulate a model using ModelSim or Incisive^® with a vector file created by the Workflow Advisor.

• Verify with Cosimulation: Cosimulate the DUT in ModelSim or Incisive with the test bench in MATLAB.

• Verify with FPGA-in-the-Loop: Create the FPGA programming file and test bench, and, optionally, download it to your selected development board.

You must have an HDL Verifier license to use these workflows.

You can now generate a report that shows how well your generated HDL code conforms to an industry coding standard. Errors and warnings in the report link to elements in your original design so you can fix problems.

You can also generate third-party lint tool scripts to use to check your generated HDL code. In this release, you can generate Leda, SpyGlass, and generic scripts.

To learn more about the coding standard report, see HDL Coding Standard Report.

To learn how to generate a coding standard report and lint tool script in the Simulink to HDL workflow, see:

• Generate an HDL Coding Standard Report

• Generate an HDL Lint Tool Script

To learn how to generate a coding standard report and lint tool script in the MATLAB to HDL workflow, see:

• Generate an HDL Coding Standard Report

• Generate an HDL Lint Tool Script

When you generate code for a subsystem within a model, the output folder structure now includes the model name.

For example, if you generate code for a subsystem in a model, Mymodel, the output folder is hdlsrc/Mymodel.

Compatibility Considerations

If you have scripts that depend on a specific output folder structure, you must update them with the new structure.

You can now specify the generated HDL test bench to use file I/O to read input stimulus and output response data during simulation, instead of including data constants in the test bench code. Doing so improves scalability for designs needing long simulations.

This feature is available when Verilog is the target language.

For details, see Test Bench Generation with File I/O.

You can now specify a prefix for every module or entity name in the generated HDL code. This feature helps you to avoid name clashes when you want to have multiple instances of the HDL code generated from the same block. For details, see ModulePrefix.

The Sqrt, Reciprocal Sqrt, reciprocal Divide, and reciprocal Math Function blocks now have a single-rate pipelined architecture. The new architecture enables you to use the high-speed Newton-Raphson algorithm without multirate or overclocking.

The following table lists each block with its new block implementation.

Effective with this release, the following System objects provide HDL code generation:

• comm.HDLCRCGenerator

• comm.HDLCRCDetector

• comm.HDLRSEncoder

• comm.HDLRSDecoder

• dsp.HDLNCO

The following blocks are now supported for HDL code generation:

• NCO HDL Optimized

• Bias

• Relay

• Dot Product

• Sum with more than two inputs with different signs

• MinMax with multiple input data types

Floating-point to fixed-point conversion now supports structures and constant value inputs.

HDL RAM System object

With release 2012b, you can use the hdlram System object for modeling and generating fixed-point code for RAMs in FPGAs and ASICs. The hdlram System object provides simulation capability in MATLAB for Dual Port, Simple Dual Port, and Single Port RAM. The System object also generates RTL code that can be inferred as a RAM by most synthesis tools.

To learn how to model and generate RAMs using the hdlram System object, see Model and Generate RAM with hdlram.

HDL System object support for biquad filters

HDL support has been added for the following System object:

• dsp.BiquadFilter

HDL support with demodulator System objects

HDL support has been added for the following System objects:

• comm.BPSKDemodulator

• comm.QPSKDemodulator

• comm.PSKDemodulator

• comm.RectangularQAMDemodulator

• comm.RectangularQAMModulator

You can now generate a MATLAB Function block during the MATLAB to HDL workflow. You can use the generated block for further design, simulation, and code generation in Simulink.

For details, see MATLAB Function Block Generation.

HDL code generation

In R2012b, HDL code generation support has been added for the following blocks:

• General CRC Syndrome Detector HDL Optimized

  For an example of using the HDL-optimized CRC generator and detector blocks, see Using HDL Optimized CRC Library Blocks.

• Integer-Input RS Encoder HDL Optimized

• Integer-Output RS Decoder HDL Optimized

Multichannel Discrete FIR filters

The Discrete FIR Filter block accepts vector input and supports multichannel implementation for better resource utilization.

• With vector input and channel sharing option on, the block supports multichannel fully parallel FIR, including direct form FIR, sym/antisym FIR, and FIRT. Support for all implementation parameters, for example: multiplier pipeline, add pipeline registers.

• With vector input and channel sharing option off, the block instantiates one filter implementation for each channel. If the input vector size is N, N identical filters are instantiated.

Applies to the fully parallel architecture option for FIR filters only.

The FPGA Board Manager and New FPGA Board Wizard allow you to add custom board information so that you can use FIL simulation with an FPGA board that is not one of the pre-registered boards. See FPGA Board Customization.

The resource sharing optimization now operates on MATLAB Function blocks. For details, see Specify Resource Sharing.

The delay balancing and distributed pipelining optimizations now operate on black box subsystems. To learn how to specify latency and enable distributed pipelining for a black box subsystem, see Customize the Generated Interface.

You can now generate a Xilinx System Generator Black Box block during the MATLAB-to-HDL workflow. You can use the generated block for further design, simulation, and code generation in Simulink.

For details, see Xilinx System Generator Black Box Block Generation.

Two new functions, hdlsaveparams and hdlrestoreparams, enable you to save and restore nondefault HDL-related model parameters. Using these functions, you can perform multiple iterations on your design to optimize the generated code.

For details, see hdlsaveparams and hdlrestoreparams.

You can now convert your MATLAB code from floating-point to fixed-point and generate HDL code using the command-line interface.

To learn how to use the command line interface, open the tutorial:

showdemo mlhdlc_tutorial_cli

You can now specify the clock enable toggle rate in your test bench to match your input data rate or improve test coverage.

To learn how to specify your test bench clock enable toggle rate, see Test Bench Clock Enable Toggle Rate Specification.

The dsp.Delay System object now maps to RAM if the RAM mapping optimization is enabled and the delay size meets the RAM mapping threshold.

To learn how to map the dsp.Delay System object to RAM, see Map Persistent Arrays and dsp.Delay to RAM.

You can now generate code for the DSP System Toolbox Repeat block in a model with multiple clocks.

With the HDL Coder HDL Workflow Advisor, you can automatically verify using your Simulink test bench with the new verification step Run Cosimulation Test Bench. During verification, the HDL Workflow Advisor and HDL Verifier verify the generated HDL using cosimulation between the HDL Simulator and the Simulink test bench. See Automatic Verification in the HDL Verifier documentation.

The Xilinx Virtex-6 FPGA ML605 board has been added for Turnkey Workflow in the HDL Workflow Advisor.

HDL Coder replaces Simulink HDL Coder and adds the HDL code generation capability directly from MATLAB.

To generate HDL code from MATLAB, you need the following products:

• HDL Coder

• MATLAB Coder

• Fixed-Point Toolbox™

• MATLAB

To generate HDL code from Simulink, you need the following products:

• HDL Coder

• MATLAB Coder

• Fixed-Point Toolbox

• Simulink Fixed Point™

• Simulink

• MATLAB

You can now generate HDL code directly from MATLAB code.

This workflow provides:

• Verilog or VHDL code generation from MATLAB code.

• Test bench generation from MATLAB scripts.

• Automated conversion from floating point code to fixed point code.

• Automated HDL verification through integration with ModelSim and ISim.

• HDL code generation for a subset of System objects from the Communications System Toolbox and DSP System Toolbox.

• A traceability report mapping generated HDL code to your original MATLAB code.

The MATLAB to HDL workflow provides the following automated HDL code optimizations:

• Area optimizations: RAM mapping for persistent array variables, loop streaming, resource sharing, and constant multiplier optimization.

• Speed optimizations: input pipelining, output pipelining, and distributed pipelining.

The coder can also generate a resource utilization report, with RAM usage and the number of adders, multipliers, and muxes in your design.

See also HDL Code Generation from MATLAB.

You can now generate HDL code from a subsystem at any level of the subsystem hierarchy. In previous releases, you could generate HDL code from the top-level subsystem only.

This feature also enables you to check any level subsystem for code generation compatibility, and to automatically generate a testbench.

You can now generate code with a flattened subsystem hierarchy, while preserving hierarchy in nested subsystems.

This option enables you to perform more extensive area and speed optimization on the flattened component. It also enables you to reduce the number of HDL output files.

See also Hierarchy Flattening.

You can now generate HDL code from the Discrete Transfer Fcn block.

For details, see Discrete Transfer Fcn Requirements and Restrictions.

A new property, ConstrainedOutputPipeline, enables you to specify the number of registers you wish to have on an output port without introducing additional delay on the input to output path. The coder redistributes existing delays within your design to try to meet the constraint. This behavior is different from the OutputPipeline property, which introduces additional delay on the input to output path.

If the coder is unable to meet the constraint using existing delays, it reports the difference between the number of desired and actual output registers in the timing report.

The Sum of Elements, Product of Elements, and MinMax blocks can now participate in distributed pipelining if their architecture is set to Tree.

Multiple Accesses to RAMs Mapped from Persistent Variables

You can now perform multiple reads and writes to a persistent variable, and the persistent variable will still be mapped to RAM. In previous releases, a RAM mapped from a persistent variable could be accessed only once.

Streaming for MATLAB Loops and Vector Operations

You can now perform streaming on MATLAB loops and loops created from vector operations for improved area efficiency.

For details, see Loop Optimization.

Loop Unrolling for MATLAB Loops and Vector Operations

You can now unroll user-written MATLAB loops and loops created from vector operations. This enables the coder to perform area and speed optimizations on the unrolled loops.

For details, see Loop Optimization.

You can now automatically generate HDL code from subsystems containing Xilinx System Generator for DSP blocks.

For details, see Code Generation with Xilinx System Generator Subsystems.

The HDL Workflow Advisor has now been tested with Altera Quartus II 11.0. In previous releases, the HDL Workflow Advisor was tested with Altera Quartus II 9.1.

The coder can now map Simulink floating point operations to synthesizable floating point Altera Megafunctions and Xilinx LogiCORE IP Floating Point Operator v5.0 blocks. To learn more, see FPGA Target-Specific Floating-Point Library Mapping.

For a list of supported Altera Megafunction blocks, see Supported Altera Floating-Point Library Blocks.

For a list of supported Xilinx LogicCORE IP blocks, see Supported Xilinx Floating-Point Library Blocks.

In the FPGA Turnkey workflow, you can now use vector data types with the Scalarize Vector Ports option to automatically generate PCI DMA transfers on the PCI interface between xPC Target and FPGA. You no longer need to manually insert multiplexers, demultiplexers and provide synchronization logic for vector data transfers.

If the Scalarize Vector Ports option is disabled when the code generation subsystem has vector ports, the coder displays an error.

There is a new global property, RAMArchitecture, that enables you to generate RAMs either with or without clock enables. This property applies to every RAM in your design, and replaces the block level property, RAMStyle. By default, RAMs are generated with clock enables.

To generate RAMs without clock enables, set RAMArchitecture to 'WithoutClockEnable'. To generate RAMs with clock enables, either use the default, or set RAMArchitecture to 'WithClockEnable'. For more information, see Implement RAMs With or Without Clock Enable.

Compatibility Considerations

The coder now ignores the block level property, RAMStyle.

If a block's RAMStyle property is set, the coder generates a warning.

HDL Workflow Advisor now supports Altera FPGA design software and the following Altera development kits and boards:

• Altera Arria II GX FPGA development kit

• Altera Cyclone III FPGA development kit

• Altera Cyclone IV GX FPGA development kit

• Altera DE2-115 development and education board

This workflow has been tested with Altera Quartus II 11.0.

Release R2012a provides HDL code generation for the Bus Creator and Bus Selector blocks. You must use these blocks for your buses if you want HDL support.

Release R2012a provides HDL code generation for the new HDL CRC Generator block.

When using filter blocks to generate HDL code, you can specify coefficients from input port(s). This feature applies to FIR and BiQuad filter blocks only. Fully Parallel and all serial architectures are supported.

Follow these directions to use programmable filters:

1. Select Input port(s) as coefficient source from the filter block mask.

2. Connect the coefficient port with a vector signal.

3. Specify the implementation architecture and parameters from the HDL Coder property interface.

4. Generate HDL code.

Notes

• For fully parallel implementations, the coefficients ports are connected to the dedicated MAC directly.

• For serial implementation, the coefficients ports first go to a mux, and then to the MAC. The mux decides the coefficients that used at current time instant

• For Discrete FIR filters, this feature is not supported under the following conditions:

  • Implementations having coefficients specified by dialog parameters (for example, complex input and coefficients with serial architecture)

  • Filters using DA architecture

  • CoeffMultipliers specified as csd or factored-csd

• For Biquad filters, this feature is not supported when CoeffMultipliers are specified as csd or factored-csd.

You can specify multiple clocks in one of the following ways:

• Use the model-level parameter ClockInputs with the function makehdl and specify the value as 'Multiple'.

• In the Clock settings section of the Global Settings pane in the HDL Code Generation Configuration Parameters dialog box, set Clock inputs to Multiple.

When you use single-clock mode, HDL code generated from multirate models uses a single master clock that corresponds to the base rate of the DUT. When you use multiple-clock mode, HDL code generated from multirate models use one clock input for each rate in the DUT. The number of timing controllers generated in multiple-clock mode depends on the design in the DUT.

The ClockInputs parameter supports the values 'Single' and 'Multiple', where the default is 'Single'. In the default single-clock mode, the coder behavior is unchanged from previous releases.

Resource reports include the HDL resource usage for filter blocks. The report includes adders, subtractors, multipliers, multiplexers, registers. This feature covers all filter blocks, and all implementations for the block.

You can turn on the report feature using the command line (ResourceReport) or GUI (Generate resource utilization report). The following illustrations show a report for a model that includes a Discrete FIR Filter block.

You can choose from several filter architectures for FIR Decimation and Discrete FIR Filter blocks. Choices are:

• Fully Parallel

• Distributed Architecture (DA)

• Fully Serial

• Party Serial

• Cascade Serial

The availability of architectures depends on the transfer function type and filter structure of filter blocks. For Partly Serial and DA, specify at least SerialPartition and DALUTPartition, respectively, so that these architectures are inferred. For example, if you select Distributed Architecture (DA), make sure to also set DALUTPartition.

HDL support for serial implementations of a FIR block with complex inputs.

External reset support added for level mode.