Output minimum or maximum input value (HDL Coder)
The MinMax block is available with Simulink®.
For information about the simulation behavior and block parameters, see MinMax.
This block has multi-cycle implementations that introduce additional latency in the generated code. To see the added latency, view the generated model or validation model. See Generated Model and Validation Model.
| Architecture | Additional cycles of latency | Description |
|---|---|---|
defaultTree | 0 | Generates a tree structure of comparators. |
Cascade | 1, when block has a single vector input port. | This implementation is optimized for latency * area, with medium speed. See Cascade Architecture Best Practices. |
Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. See also ConstrainedOutputPipeline.
Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also InputPipeline.
Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also OutputPipeline.
Generate a VHDL® entity or Verilog® module for
each cascade stage. The default is off.
See also InstantiateStages.
Specify partitions for Cascade-serial implementations as a vector of the lengths of each partition. The default setting uses the minimum number of stages. See also SerialPartition.