HDL Coder™ native floating-point technology can generate HDL code from your floating-point design. These are some of the key features:
Generation of target-independent HDL code that you can deploy on any FPGA or ASIC
Support for the full range of IEEE-754 features including denormal numbers, exceptions, and rounding modes
Extensive support for math and trigonometric blocks
Floating-point designs have better precision, higher dynamic range, and a shorter development cycle than fixed-point designs. If your design has complex math and trigonometric operations, use native floating-point technology.
| NativeFloatingPoint | Generate target-independent HDL code from single-precision floating-point models |
| ShareFloatingPointIP | Share floating-point IP blocks with the resource sharing optimization |
| FPToleranceStrategy | Specify whether to check for floating-point tolerance based on relative error or ULP error |
| FPToleranceValue | Enter the tolerance value based on floating-point tolerance check setting |
HDL Coder Native Floating-Point Support
HDL code generation from floating-point models and design considerations.
Generate Target-Independent HDL Code with Native Floating-Point
How to generate HDL code from floating-point models.
Numerical Considerations with Native Floating-Point
Numerical considerations when generating code with native floating-point and IEEE-754 compliance.
Latency Customization with Native Floating-Point
Latency considerations when generating code from floating-point models.
Verify the Generated Code from Native Floating-Point
How you can verify the generated code from the floating-point model using HDL Testbench, Cosimulation, and FPGA-in-the-loop.
Operators and Simulink Blocks Supported for Native Floating-Point
List of operators and supported blocks in the floating-point model.