Resettable Synchronous Subsystem
Represent subsystem that has synchronous reset and enable behavior (HDL Coder)
Description
The Resettable Synchronous Subsystem block is available in the HDL Subsystems block library in HDL Coder™. For information about the simulation behavior and block parameters, see Resettable Synchronous Subsystem.
The Resettable Synchronous Subsystem uses the State Control block in Synchronous mode with the Resettable Subsystem block. For subsystem blocks with state, the State Control block in Synchronous mode provides efficient reset and enable simulation behavior on hardware.
The reset
port in the Resettable Synchronous Subsystem block
adds reset capability to blocks inside the subsystem that have state.
This includes blocks that need not have an external reset port capability,
such as filters, Stateflow® Chart, and MATLAB
Function blocks. For HDL code generation, the Reset
trigger type of the Reset port is set to level
hold by default.
HDL Architecture
| Architecture | Description |
|---|---|
Module (default) | Generate code for the subsystem and the blocks within the subsystem. |
BlackBox | Generate a black box interface. The generated HDL code includes only the input/output port definitions for the subsystem. This way, you can use a subsystem in your model to generate an interface to existing, manually written HDL code. The black-box interface generation for subsystems is similar to the Model blocks interface generation without the clock signals. |
| Remove the subsystem from the generated code. You can use the subsystem in simulation, however, treat it as a "no-op" in the HDL code. |
Black Box Interface Customization
For the BlackBox architecture, you
can customize port names and set attributes of the external component
interface. See Customize Black Box or HDL Cosimulation Interface.
HDL Block Properties
General
- AdaptivePipelining
Automatic pipeline insertion based on the synthesis tool, target frequency, and multiplier word-lengths. The default is
inherit. See alsoAdaptivePipelining.- BalanceDelays
Detects introduction of new delays along one path, and inserts matching delays on the other paths. The default is
inherit. See also BalanceDelays.- ClockRatePipelining
Insert pipeline registers at faster clock rate instead of the slower data rate. The default is
inherit. See alsoClockRatePipelining.- ConstrainedOutputPipeline
Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. See also ConstrainedOutputPipeline.
- DistributedPipelining
Pipeline register distribution, or register retiming. The default is
off. See also DistributedPipelining.- DSPStyle
Synthesis attributes for multiplier mapping. The default is
none. See also DSPStyle.- FlattenHierarchy
Remove subsystem hierarchy from generated HDL code. The default is
inherit. See also FlattenHierarchy.- InputPipeline
Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also InputPipeline.
- OutputPipeline
Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also OutputPipeline.
- SharingFactor
Number of functionally equivalent resources to map to a single shared resource. The default is 0. See also Resource Sharing.
- StreamingFactor
Number of parallel data paths, or vectors, that are time multiplexed to transform into serial, scalar data paths. The default is 0, which implements fully parallel data paths. See also Streaming.
Target Specification
If this block is not the DUT, the block property settings in the Target Specification tab are ignored.
In the HDL Workflow Advisor, if you use the IP Core Generation
workflow, these target specification block property values are saved
with the model. If you specify these target specification block property
values using hdlset_param, when you open HDL
Workflow Advisor, the fields are populated with the corresponding
values.
- ProcessorFPGASynchronization
Processor/FPGA synchronization mode, specified as a character vector.
You can set this property In the HDL Workflow Advisor, in the Processor/FPGA Synchronization field.
Values:
Free running(default) |Coprocessing - blockingExample:
'Free running'- IPCoreAdditionalFiles
Verilog® or VHDL® files for black boxes in your design. Specify the full path to each file, and separate file names with a semicolon (;).
You can set this property in the HDL Workflow Advisor, in the Additional source files field.
Values:
''(default) | character vectorExample:
'C:\myprojfiles\led_blinking_file1.vhd;C:\myprojfiles\led_blinking_file2.vhd;'- IPCoreName
IP core name, specified as a character vector.
You can set this property in the HDL Workflow Advisor, in the IP core name field. If this property is set to the default value, the HDL Workflow Advisor constructs the IP core name based on the name of the DUT.
Values:
''(default) | character vectorExample:
'my_model_name'- IPCoreVersion
IP core version number, specified as a character vector.
You can set this property in the HDL Workflow Advisor, in the IP core version field. If this property is set to the default value, the HDL Workflow Advisor sets the IP core version.
Values:
''(default) | character vectorExample:
'1.3'
Restrictions
You cannot use the State Control block in Classic mode or remove the State Control block from the Resettable Synchronous Subsystem block.
The Reset trigger type of the Reset port inside the subsystem must be set to
level hold.A Delay block with nonvirtual bus input signals inside a Resettable Synchronous Subsystem is not supported if you enable optimizations on the subsystem.
HDL Coder does not support these blocks inside a Resettable Synchronous Subsystem:
DSP System Toolbox
Biquad Filter
FFT HDL Optimized
IFFT HDL Optimized
NCO HDL Optimized
Communications System Toolbox
Convolutional Encoder
Viterbi Decoder
PN Sequence Generator
Integer-Output RS Decoder HDL Optimized
Vision HDL Toolbox
Demosaic Interpolator
Edge Detector
Histogram
Image Filter
Median Filter
Binary and Grayscale Morphology blocks