Implement fixed-point sine wave optimized for HDL code generation
The Sine HDL Optimized block is available in the Lookup Tables library in HDL Coder™. For information about the simulation behavior and block parameters, see Sine HDL Optimized.
For the most efficient HDL implementation, configure the block with an exact power of two as the number of elements. In the Block Parameters dialog box, for Number of data points, specify an integer that is an exact power of two. By default, the Number of data points is 64.
When you specify a power of two for the Number of data points, the lookup tables precede a register without reset after HDL code generation. The combination of the lookup table block and register without reset map efficiently to RAM on the target device.
The HDL code implements the Sine HDL Optimized block by using the quarter-wave lookup table that you specify in the Simulink® block parameters.
To generate code that is optimized for area and speed, for Number
of data points, enter (2^. n)n is
an integer.
Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. See also ConstrainedOutputPipeline.
Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also InputPipeline.
Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also OutputPipeline.