hdlcoder.ReferenceDesign class

Package: hdlcoder

Reference design registration object that describes SoC reference design

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Description

refdesign = hdlcoder.ReferenceDesign('SynthesisTool', toolname) creates a reference design object that you use to register a custom reference design for an SoC platform.

To specify the characteristics of your reference design, set the properties of the reference design object.

Use a reference design tool version that is compatible with the supported tool version. If you choose a different tool version, it is possible that HDL Coder™ is unable to create the reference design project for IP core integration.

Construction

refdesign = hdlcoder.ReferenceDesign('SynthesisTool',toolname) creates a reference design object that you use to register a custom reference design for an SoC platform.

Input Arguments

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Synthesis tool name, specified as a character vector.

Example: 'Altera Quartus II'

Properties

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Reference design name, specified as a character vector. In the HDL Workflow Advisor, this name appears in the Reference design dropdown list.

Example: 'Default system (Vivado 2015.4)'

Board associated with this reference design, specified as a character vector.

Example: 'Enclustra Mars ZX3 with PM3 base board'

One or more tool versions that work with this reference design, specified as a cell array of character vectors.

Example: {'2015.4'}

Example: {'13.7','14.0'}

One or more design constraint files, specified as a cell array of character vectors. This property is optional.

Example: {'MarsZX3_PM3.xdc'}

Example: {'MyDesign.qsf'}

One or more relative paths to files or folders that the reference design requires, specified as a cell array of character vectors. This property is optional.

Examples of required files or folders:

  • Existing IP core used in the reference design.

    For example, if the IP core, my_ip_core, is in the reference design folder, set CustomFiles to {'my_ip_core']

  • PS7 definition XML file.

    For example, to include a PS7 definition XML file, ps7_system_prj.xml, in a folder, data, set CustomFiles to {fullfile('data', 'ps7_system_prj.xml')}

  • Folder containing existing IP cores used in the reference design. HDL Coder only supports a specific IP core folder name for each synthesis tool:

    • For Altera® Qsys, IP core files must be in a folder named ip. Set CustomFiles to {'ip'}.

    • For Xilinx® Vivado®, IP core files, or a zip file containing the IP core files, must be in a folder named ipcore. Set CustomFiles to {'ipcore'}.

    • For Xilinx EDK, IP core files must be in a folder named pcores. Set CustomFiles to {'pcores'}.

Example: {'my_ip_core'}

Example: {fullfile('data', 'ps7_system_prj.xml')}

Example: {'ip'}

Example: {'ipcore'}

Example: {'pcores'}

Methods

addAXI4SlaveInterfaceAdd and define AXI4 slave interface
addClockInterfaceAdd clock and reset interface
addCustomEDKDesignSpecify Xilinx EDK MHS project file
addCustomQsysDesignSpecify Altera Qsys project file
addCustomVivadoDesignSpecify Xilinx Vivado exported block design Tcl file
addInternalIOInterfaceAdd and define internal IO interface between generated IP core and existing IP cores
addParameterAdd and define custom parameters for your reference design
CallbackCustomProgrammingMethodFunction handle for custom callback function that gets executed during Program Target Device task in the Workflow Advisor
EmbeddedCoderSupportPackageSpecify whether to use an Embedded Coder support package
PostBuildBitstreamFcnFunction handle for callback function that gets executed after Build FPGA Bitstream task in the HDL Workflow Advisor
PostCreateProjectFcnFunction handle for callback function that gets executed after Create Project task in the HDL Workflow Advisor
PostSWInterfaceFcnFunction handle for custom callback function that gets executed after Generate Software Interface Model task in the HDL Workflow Advisor
PostTargetInterfaceFcnFunction handle for callback function that gets executed after Set Target Interface task in the HDL Workflow Advisor
PostTargetReferenceDesignFcnFunction handle for callback function that gets executed after Set Target Reference Design task in the HDL Workflow Advisor
validateReferenceDesignCheck property values in reference design object

See Also

Related Examples

More About

Introduced in R2015a

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