Model and Architecture Design
Supported blocks, best practices, design patterns,
compatibility checks, clocks and reset
- Model Design
Create supported block library, check compatibility,
design models
- Supported Blocks
HDL block implementations and code generation restrictions
- Block Configuration
Block implementation specification, model configuration
- Clocking and Multirate Design
Clock generation, HDL code generation guidelines for
multirate models
- External Component Interfaces
HDL code instantiation, black box interfaces, Xilinx® System
Generator, Altera® DSP Builder, HDL cosimulation
- Native Floating Point
What is HDL Coder native floating-point, the various
features supported, how to model your design, generate HDL code, and
verify the generated code