HDL Coder Native Floating-Point Support

HDL Coder™ native floating-point technology can generate HDL code from your floating-point design. Floating-point designs have better precision, higher dynamic range, and a shorter development cycle than fixed-point designs. If your design has complex math and trigonometric operations, use native floating-point technology.

Why Use Native Floating-Point?

In your Simulink^® model:

You can have single-precision floating-point data types and operations.
You can have a combination of integer, fixed-point, and floating-point operations. By using Data Type Conversion blocks, you can perform conversions between single-precision and fixed-point data types.

The generated code:

Complies with the IEEE-754 standard of floating-point arithmetic.
Is target-independent. You can deploy the code on any generic FPGA or an ASIC.
Does not require floating-point processing units or hard floating-point DSP blocks on the target ASIC or FPGA.

HDL Coder provides support for:

Math and trigonometric functions, and a large subset of Simulink blocks
Denormal numbers
Customizing the latency of the floating-point operator

Numerical Considerations and IEEE-754 Standard Compliance

HDL Coder generates code in compliance with the IEEE 754–2008 standard of floating-point arithmetic.

In the IEEE 754–2008 standard, the single-precision floating-point number is 32-bit in size. The 32-bit number encodes a 1-bit sign, an 8-bit exponent, and a 23-bit mantissa.

This graph is the normalized representation for floating-point numbers. You can compute the actual value of a normal number as:

$v a l u e = {(- 1)}^{s i g n} * (1 + \underset{i = 1}{\overset{23}{Σ}} b_{23 - i} 2^{- i}) * 2^{(e - 127)}$

The exponent field represents the exponent plus a bias of 127. The size of the mantissa is 24 bits. The leading bit is a 1, so the representation encodes the lower 23 bits.

To generate code that complies with the IEEE-754 standard, HDL Coder supports:

Round to nearest rounding mode
Denormal numbers
Exceptions such as NaN (Not a Number), Inf, and Zero
Customization of ULP (Units in the Last Place) and relative accuracy

For more information, see Numerical Considerations with Native Floating-Point.

Latency Customization

When generating code from your floating-point algorithm, you can customize the latency of the floating-point operator.

Latency Strategy setting: Specify whether to map your Simulink model to maximum, minimum, or zero latency of the floating-point operator.
Oversampling factor: The design operates at a faster clock-rate and absorbs the clock-rate pipelines with the latency of the floating-point operator.
Delay blocks in the model: If your Simulink model has a latency, HDL Coder can absorb some or all of the latency with the native floating-point implementation.

Documentation