Documentation

When you select Generate resource utilization report, HDL Coder™ adds a Code Generation Report that has a Code Interface Report and a Timing and Area Report section.

The Code Interface Report shows the DUT input and output port names, data types, and bit widths. The Timing and Area Report section has two subsections:

• High-level Resource Report: Summarizes multipliers, adders/subtractors, and registers consumed by the device under test (DUT). Includes a detailed report on the resources that each subsystem uses. Wherever possible, the detailed report links back to corresponding blocks in your model.

• Target-Specific Report: When you request target-specific code generation on the model, this subsection shows the resource utilization report.

Code Interface Report

The Code Interface Report shows the DUT input and output port names, data types, and bit widths. The report displays a link corresponding to each input and output port in your Simulink^® model.

High-Level Resource Report

The High-Level Resource report analyzes the effects of optimizations, such as resource sharing and streaming and displays a summary of the resources that your DUT uses. The report shows the number of 1–bit registers and I/O bits and includes resource usage for model references.

The total number of 1–bit Registers is calculated as a sum of products over the bit widths of the registers and their frequency of occurrence. To calculate the total 1–bit registers, refer to the Registers section in the Detailed Report. For this example, $$\text{Total 1-bit Registers }=(8\text{x4})+(32\text{x24})\text{ = 800}$$.

Target-Specific Report

When you map the Simulink model to a floating-point target library, the Target-Specific report shows the resource utilization.

See also Generate HDL Code for FPGA Floating-Point Target Libraries.