Before generating code, HDL Coder™ creates a behavioral model of the HDL code, called the generated model. The generated model uses HDL-specific block implementations, and it implements the area and speed optimizations that you specify in your Simulink® model.
The generated model is an intermediate model that shows latency and numeric differences between your Simulink DUT and the generated HDL code. Delays that the coder inserts are highlighted in the generated model.
After code generation, the generated model is saved in the target
folder. By default, the generated model prefix is gm_.
For example, if your model name is myModel,
your generated model name is gm_myModel.
| Highlight Color | Delay Type |
|---|---|
| Cyan | Block implementation RAM mapping |
| Green | Constrained output pipelining |
| Orange | Distributed pipelining Input and output pipelining Delay balancing Clock-rate pipelining |
Some block architectures and optimizations introduce latency. For example, for the Reciprocal block, you can specify HDL block architectures that implement the Newton-Raphson method. The Newton-Raphson method is iterative, so block architectures that use it are multicycle and introduce latency at the block rate.
Similarly, the resource sharing area optimization time-multiplexes data over a shared hardware resource, which introduces local multirate and latency at the upsampled rate.
HDL block architectures can introduce numeric differences. For example:
The Newton-Raphson method is an approximation, so if you select a Newton-Raphson block implementation, the generated model shows a change in numerics.
HDL implementations for signal processing blocks, such as filters, can change numerics.
See also Locate Numeric Differences After Speed Optimization.
To customize the generated model, use the following properties
with makehdl or hdlset_param:
Because the generated model is often substantially different from the original model, the coder can also create a validation model to compare the original model with the generated model. The validation model inserts delays at the outputs of the original model to compensate for latency differences, and compares the outputs of the two models. When you simulate the validation model, numeric differences in the output data trigger an assertion.
Using the validation model, you can verify that the output of the optimized DUT is bit-true to the results produced by the original DUT.
A validation model contains:
A generated model.
An original model, with compensating delays inserted.
Original inputs, routed to both the original model and generated model.
Scopes for comparing and viewing the outputs of the original model and generated model.
To generate a validation model:
In the Configuration Parameters dialog box, in the HDL Code Generation pane, enable Generate validation model.
In the HDL Workflow Advisor, in the HDL Code Generation > Generate RTL Code and Testbench pane, enable Generate validation model.
Use the GenerateValidationModel property
with makehdl or hdlset_param.