Documentation

Test Bench Overview

The Test Bench pane lets you set options that determine characteristics of generated test bench code.

Generate Test Bench Button

The Generate Test Bench button initiates test bench generation for the system selected in the Generate HDL for menu. See also makehdltb.

HDL test bench

Enable or disable HDL test bench generation.

Settings

Tar

Dependencies

This check box enables the options in the Configuration section of the Test Bench pane.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

Generating VHDL Test Bench Code

Cosimulation blocks

Generate a model containing HDL Cosimulation block(s) for use in testing the DUT.

Settings

Default: Off

On

When you select this option, HDL Coder™ generates and opens a model that contains one or more HDL Cosimulation blocks. The coder generates cosimulation blocks if your installation includes one or more of the following:

• HDL Verifier™ for use with Mentor Graphics^® ModelSim^®

• HDL Verifier for use with Cadence Incisive^®

The coder configures the generated HDL Cosimulation blocks to conform to the port and data type interface of the DUT selected for code generation. By connecting an HDL Cosimulation block to your model in place of the DUT, you can cosimulate your design with the desired simulator.

Off

Do not generate HDL Cosimulation blocks.

Dependencies

This check box enables the other options in the Configuration section of the Test Bench pane.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

GenerateCoSimBlock

Cosimulation model for use with:

Specify the HDL cosimulator for use with the generated HDL Cosimulation block and model

Settings

Default: Mentor Graphics ModelSim

Select one of the following options from the dropdown menu:

• Mentor Graphics ModelSim: This option is the default. HDL Coder generates and opens a Simulink^® model that contains an HDL Cosimulation block specifically for use with Mentor Graphics ModelSim.

• Cadence Incisive: The coder generates and opens a Simulink model that contains an HDL Cosimulation block specifically for use with Cadence Incisive.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

GenerateCoSimModel

Test bench name postfix

Specify a suffix appended to the test bench name.

Settings

Default: _tb

For example, if the name of your DUT is my_test, HDL Coder adds the default postfix _tb to form the name my_test_tb.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

TestBenchPostFix

Force clock

Specify whether the test bench forces clock input signals.

Settings

Default: On

On

The test bench forces the clock input signals. When this option is selected, the clock high and low time settings control the clock waveform.

Off

A user-defined external source forces the clock input signals.

Dependencies

This property enables the Clock high time and Clock high time options.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

ForceClock

Clock high time (ns)

Specify the period, in nanoseconds, during which the test bench drives clock input signals high (1).

Settings

Default: 5

The Clock high time and Clock low time properties define the period and duty cycle for the clock signal. Using the defaults, the clock signal is a square wave (50% duty cycle) with a period of 10 ns.

Dependency

This parameter is enabled when Force clock is selected.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

ClockHighTime

Clock low time (ns)

Specify the period, in nanoseconds, during which the test bench drives clock input signals low (0).

Settings

Default: 5

The Clock high time and Clock low time properties define the period and duty cycle for the clock signal. Using the defaults, the clock signal is a square wave (50% duty cycle) with a period of 10 ns.

Dependency

This parameter is enabled when Force clock is selected.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

ClockLowTime

Hold time (ns)

Specify a hold time, in nanoseconds, for input signals and forced reset input signals.

Settings

Default: 2 (given the default clock period of 10 ns)

The hold time defines the number of nanoseconds that reset input signals and input data are held past the clock rising edge. The hold time is expressed as a positive integer or double (with a maximum of 6 significant digits after the decimal point).

Tips

• The specified hold time must be less than the clock period (specified by the Clock high time and Clock low time properties).

• This option applies to reset input signals only if Force reset is selected.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

HoldTime

Setup time (ns)

Display setup time for data input signals.

Settings

Default: None

This is a display-only field, showing a value computed as (clock period - HoldTime) in nanoseconds.

Dependency

The value displayed in this field depends on the clock rate and the values of the Hold time property.

Command-Line Information

Because this is a display-only field, a corresponding command-line property does not exist.

See Also

HoldTime

Force clock enable

Specify whether the test bench forces clock enable input signals.

Settings

Default: On

On

The test bench forces the clock enable input signals to active-high (1) or active-low (0), depending on the setting of the clock enable input value.

Off

A user-defined external source forces the clock enable input signals.

Dependencies

This property enables the Clock enable delay (in clock cycles) option.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

ForceClockEnable

Clock enable delay (in clock cycles)

Define elapsed time (in clock cycles) between deassertion of reset and assertion of clock enable.

Settings

Default: 1

The Clock enable delay (in clock cycles) property defines the number of clock cycles elapsed between the time the reset signal is deasserted and the time the clock enable signal is first asserted. In the figure below, the reset signal (active-high) deasserts after 2 clock cycles and the clock enable asserts after a clock enable delay of 1 cycle (the default).

Dependency

This parameter is enabled when Force clock enable is selected.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

TestBenchClockEnableDelay

Force reset

Specify whether the test bench forces reset input signals.

Settings

Default: On

On

The test bench forces the reset input signals.

Off

A user-defined external source forces the reset input signals.

Tips

If you select this option, you can use the Hold time option to control the timing of a reset.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

ForceReset

Reset length (in clock cycles)

Define length of time (in clock cycles) during which reset is asserted.

Settings

Default: 2

The Reset length (in clock cycles) property defines the number of clock cycles during which reset is asserted. Reset length (in clock cycles) must be an integer greater than or equal to 0. The following figure illustrates the default case, in which the reset signal (active-high) is asserted for 2 clock cycles.

Dependency

This parameter is enabled when Force reset is selected.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

ResetLength

Hold input data between samples

Specify how long subrate signal values are held in valid state.

Settings

Default: On

On

Data values for subrate signals are held in a valid state across N base-rate clock cycles, where N is the number of base-rate clock cycles that elapse per subrate sample period. (N >= 2.)

Off

Data values for subrate signals are held in a valid state for only one base-rate clock cycle. For the subsequent base-rate cycles, data is in an unknown state (expressed as 'X') until leading edge of the next subrate sample period.

Tip

In most cases, the default (On) is the best setting for Hold input data between samples. This setting matches the behavior of a Simulink simulation, in which subrate signals are held valid through each base-rate clock period.

In some cases (for example modeling memory or memory interfaces), it is desirable to clear Hold input data between samples. In this way you can obtain diagnostic information about when data is in an invalid ('X') state.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

HoldInputDataBetweenSamples

Initialize test bench inputs

Specify initial value driven on test bench inputs before data is asserted to DUT.

Settings

Default: Off

On

Initial value driven on test bench inputs is'0'.

Off

Initial value driven on test bench inputs is 'X' (unknown).

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

InitializeTestBenchInputs

Multi-file test bench

Divide generated test bench into helper functions, data, and HDL test bench code files.

Settings

Default: Off

On

Write separate files for test bench code, helper functions, and test bench data. The file names are derived from the name of the DUT, the Test bench name postfix property, and the Test bench data file name postfix property as follows:

DUTname_TestBenchPostfix_TestBenchDataPostfix

For example, if the DUT name is symmetric_fir, and the target language is VHDL^®, the default test bench file names are:

• symmetric_fir_tb.vhd: test bench code

• symmetric_fir_tb_pkg.vhd: helper functions package

• symmetric_fir_tb_data.vhd: data package

If the DUT name is symmetric_fir and the target language is Verilog^®, the default test bench file names are:

• symmetric_fir_tb.v: test bench code

• symmetric_fir_tb_pkg.v: helper functions package

• symmetric_fir_tb_data.v: test bench data

Off

Write a single test bench file containing the HDL test bench code, helper functions, and test bench data.

Dependency

When this property is selected, Test bench data file name postfix is enabled.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

MultifileTestBench

Test bench reference postfix

Specify a character vector to be appended to names of reference signals generated in test bench code.

Settings

Default: '_ref'

Reference signal data is represented as arrays in the generated test bench code. The character vector specified by Test bench reference postfix is appended to the generated signal names.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

TestBenchReferencePostFix

Test bench data file name postfix

Specify suffix added to test bench data file name when generating multi-file test bench.

Settings

Default:'_data'

HDL Coder applies the Test bench data file name postfix character vector only when generating a multi-file test bench (i.e., when Multi-file test bench is selected).

For example, if the name of your DUT is my_test, and Test bench name postfix has the default value _tb, the coder adds the postfix _data to form the test bench data file name my_test_tb_data.

Dependency

This parameter is enabled by Multi-file test bench.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

TestBenchDataPostFix

Use file I/O to read/write test bench data

Create and use data files for reading and writing test bench input and output data.

Settings

Default: On

On

Create and use data files for reading and writing test bench input and output data.

Off

Use constants in the test bench for DUT stimulus and reference data.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

UseFileIOInTestBench

Ignore output data checking (number of samples)

Specify number of samples during which output data checking is suppressed.

Settings

Default: 0

The value must be a positive integer.

When the value of Ignore output data checking (number of samples), N, is greater than zero, the test bench suppresses output data checking for the first N output samples after the clock enable output (ce_out) is asserted.

When using pipelined block implementations, output data may be in an invalid state for some number of samples. To avoid spurious test bench errors, determine this number and set Ignore output data checking (number of samples) accordingly.

Be careful to specify N as a number of samples, not as a number of clock cycles. For a single-rate model, these are equivalent, but they are not equivalent for a multirate model.

You should use Ignore output data checking (number of samples) in cases where there is a state (register) initial condition in the HDL code that does not match the Simulink state, including the following specific cases:

• When you set the DistributedPipelining property to 'on' for the MATLAB Function block (see Distributed Pipeline Insertion for MATLAB Function Blocks)

• When you set the ResetType property to 'None' for the following blocks:

  • commcnvintrlv2/Convolutional Deinterleaver

  • commcnvintrlv2/Convolutional Interleaver

  • commcnvintrlv2/General Multiplexed Deinterleaver

  • commcnvintrlv2/General Multiplexed Interleaver

  • dspsigops/Delay

  • simulink/Additional Math & Discrete/Additional Discrete/Unit Delay Enabled

  • simulink/Commonly Used Blocks/Unit Delay

  • simulink/Discrete/Delay

  • simulink/Discrete/Memory

  • simulink/Discrete/Tapped Delay

  • simulink/User-Defined Functions/MATLAB Function

  • sflib/Chart

  • sflib/Truth Table

• When generating a black box interface to existing manually written HDL code

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

IgnoreDataChecking

Floating point tolerance check based on

When you map your design to the native floating-point libraries or the floating-point target libraries, specify the floating-point tolerance check option.

Settings

Default: relative error

Select one of these options from the dropdown menu:

• relative error: This is the default option. When you verify the generated code by using HDL Testbench, HDL Coder checks for the floating-point tolerance of the native floating-point library or the floating-point target library that your design mapped to based on the relative error.

• ulp error: When you verify the generated code by using HDL Testbench, HDL Coder checks for the floating-point tolerance of the native floating-point library or the floating-point target library that your design mapped to based on the ULP error.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

FPToleranceStrategy

Tolerance Value

Enter the tolerance value based on the floating-point tolerance check setting that you specify.

Settings

Default: 1e-07

The value must be a positive integer or a double data type.

The default tolerance value depends on the floating-point tolerance check setting that you specify. When you set the Floating point tolerance check based on to:

• relative error, the default is a Tolerance Value of 1e-07. When you use this floating-point tolerance check setting, specify the tolerance value as a double data type. You can specify a Tolerance Value, N, that is less than or equal to 1e-07.

• ulp error, the default is a Tolerance Value of 0. When you use this floating-point tolerance check setting, specify the tolerance value as an integer. You can specify a Tolerance Value, N, that is greater than or equal to 0.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

FPToleranceValue

Simulation library path

Specify the path to your compiled Altera^® or Xilinx^® simulation libraries.

Settings

Default:''

Specify the path to the compiled Altera or Xilinx simulation libraries. Altera provides the simulation model files in \quartus\eda\sim_lib folder.

Command-Line Information

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

See Also

SimulationLibPath