Check Your Model for HDL Compatibility

How to check your models for HDL code generation compatibility

Show Blocks Supported for HDL Code Generation

Find HDL code generation supported blocks

Generate a Supported Blocks Report

Summary of blocks supported in the current release

Prepare Simulink Model For HDL Code Generation

Prepare your Simulink^® model for HDL code generation

Simulink Templates for HDL Code Generation

Simulink templates for HDL code generation show how to model hardware components for efficient HDL code generation and FPGA mapping

Generate Code with Annotations or Comments

How to add annotations to generated HDL code using the DocBlock and model annotations

System Design with HDL Code Generation from MATLAB and Simulink

This example shows how to generate a MATLAB Function block from a MATLAB® design for system simulation, code generation, and FPGA programming in Simulink®.

Model Referencing for HDL Code Generation

Model referencing in your DUT subsystem enables you to:

Generate DUT Ports for Tunable Parameters

Generate DUT ports for tunable parameters

Generate Parameterized Code for Referenced Models

Generate VHDL^® generic or Verilog^® parameter for model arguments in a model reference

Generate Reusable Code for Atomic Subsystems

Generate shared code for identical subsystems or subsystems identical except for their mask parameter values

Generating HDL Code for Subsystems with Array of Buses

Generate HDL code for subsystems that use array of buses in the design