| HoldInputDataBetweenSamples | Specify how long subrate signal values are held in valid state |
| Oversampling | Specify frequency of global oversampling clock as a multiple of model base rate |
| ClockInputs | Specify generation of single or multiple clock inputs |
| OptimizeTimingController | Optimize timing controller entity by implementing separate counters per rate |
| TimingControllerArch | Generate reset for timing controller |
| MaxOversampling | Limit the maximum sample rate |
| MaxComputationLatency | Specify the maximum number of time steps for which your DUT inputs are guaranteed to be stable |
Using Multiple Clocks in HDL Coder™
This example shows how to instantiate multiple top-level synchronous clock input ports in HDL Coder.
Generate a Global Oversampling Clock
In many designs, the DUT is not self-contained.
Use Trigger As Clock in Triggered Subsystems
How to use TriggerAsClock
Generate Reset for Timing Controller
How to generate reset for timing controller
Code Generation from Multirate Models
Overview of HDL code generation for single-clock, single-tasking multirate models
Multirate Model Requirements for HDL Code Generation
Guidelines for setting up multirate models and blocks for HDL code generation
Timing Controller for Multirate Models
A timing controller entity generates the required rates from a single master clock, using one or more counters to create multiple clock enables.