Search Help
Documentation
Toggle navigation
Documentation Home
HDL Coder
Examples
Blocks and Other Reference
Release Notes
PDF Documentation
HDL Code Generation from Simulink
Model and Architecture Design
Code Generation
Verification
Verification Basics
HDL Test Bench
FPGA-in-the-Loop
Cosimulation
Deployment
Speed and Area Optimization
Reports and Scripts
Verification
Simulation and verification of generated HDL code against original model, FPGA-in-the-loop
Verification Basics
View differences between original model and HDL implementation
HDL Test Bench
Generate HDL test bench for simulation
FPGA-in-the-Loop
Test design in hardware (requires HDL Verifier™)
Cosimulation
HDL cosimulation with Simulink
®
(requires HDL Verifier)
Was this topic helpful?
HDL Coder Documentation
Examples
Blocks and Other Reference
Release Notes
PDF Documentation
Other Documentation
MATLAB
Simulink
HDL Verifier
Fixed-Point Designer
Vision HDL Toolbox
DSP System Toolbox
Documentation Home
Support
MATLAB Answers
Installation Help
Bug Reports
Product Requirements
Software Downloads