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This example shows a simple case where the VHDL^® implementation of a block introduces delays that cause a numerical mismatch between the original DUT and the generated model and HDL code. The example then demonstrates how to use delay balancing to fix the mismatch.

The following figure shows the DUT for the ex_rsqrt_delaybalancing model. The DUT is a simple multirate subsystem that includes a Reciprocal Square Root block, Sqrt. A Rate Transition block downsamples the output signal to a lower sample rate.

Generate HDL code without delay balancing and generate a validation model:

Examination of the generated model shows that HDL Coder™ has implemented the Sqrt block as a subsystem:

The following figure shows that the generated Sqrt subsystem introduces a total of 5 cycles of delay. (This behavior is inherent to the Reciprocal Square Root block implementation.) These delays map to registers in the generated HDL code when UseRAM is off.

The scope in the following figure shows the results of a comparison run between the original and generated models. The scope displays the following signals, in descending order:

• The outputs from the original model

• The outputs from the generated model

• The difference between the two

The difference is nonzero, indicating a numerical mismatch between the original and generated models.

Two factors cause this discrepancy:

• The input signal branches into two parallel paths (to the Sqrt and product blocks) but only the branch to the Sqrt block introduces delays.

• The downsampling caused by the rate transition drops samples.

You can solve these problems by manually inserting delays in the generated model. However, using delay balancing produces more consistent results.

Generate HDL code with delay balancing and generate a validation model:

The following figure shows the validation model. The lower subsystem is identical to the original DUT. The upper subsystem represents the HDL implementation of the DUT.

The upper subsystem (shown in the following figure) represents the HDL implementation of the DUT. To balance the 5-cycle delay from the Sqrt subsystem, HDL Coder has inserted a 5-cycle delay on the parallel data path. The coder has also inserted a 3-cycle delay before the Rate Transition to offset the effect of downsampling.