Hierarchy Flattening

Flatten subsystem hierarchy to enable more extensive area and speed optimization.

Adaptive Pipelining

Automatic pipeline insertion based on the synthesis tool, target frequency, and multiplier word-lengths.

Clock-Rate Pipelining

Pipeline registers insertion at the faster clock rate instead of the slower data rate.

Optimization with Constrained Overclocking

Optimization with constrained overclocking and how it works

Maximum Oversampling Ratio

The Max oversampling ratio is the maximum ratio of the final design implementation sample rate to the original sample rate.

Maximum Computation Latency

The Max computation latency parameter enables you to specify a time budget for HDL Coder™ when performing a single computation.

Delay Balancing

Insert matching delays along all data paths

Find Feedback Loops

Highlight feedback loops that are inhibiting optimizations

Resolve Numerical Mismatch with Delay Balancing

This example shows a simple case where the VHDL^® implementation of a block introduces delays that cause a numerical mismatch between the original DUT and the generated model and HDL code.