Insert matching delays along all data paths
Resolve Numerical Mismatch with Delay Balancing
This example shows a simple case where the VHDL® implementation of a block introduces delays that cause a numerical mismatch between the original DUT and the generated model and HDL code.
Locate Numeric Differences After Speed Optimization
Model generation case study showing numeric differences between original and generated models
Generated Model and Validation Model
Describes the generated model, an intermediate model that shows the HDL implementation architecture and includes latency
Blocks that belong to the blocksets and toolboxes in the following list should not be directly connected to the DUT.