Represent subsystem that has synchronous reset and enable behavior (HDL Coder)
The Synchronous Subsystem block is available with Simulink®.
For information about the simulation behavior and block parameters, see Synchronous Subsystem.
| Architecture | Description |
|---|---|
Module (default) | Generate code for the subsystem and the blocks within the subsystem. |
BlackBox | Generate a black box interface. The generated HDL code includes only the input/output port definitions for the subsystem. This way, you can use a subsystem in your model to generate an interface to existing, manually written HDL code. The black-box interface generation for subsystems is similar to the Model blocks interface generation without the clock signals. |
| Remove the subsystem from the generated code. You can use the subsystem in simulation, however, treat it as a "no-op" in the HDL code. |
For the BlackBox architecture, you
can customize port names and set attributes of the external component
interface. See Customize Black Box or HDL Cosimulation Interface.
Automatic pipeline insertion based on the synthesis tool, target
frequency, and multiplier word-lengths. The default is inherit.
See also AdaptivePipelining.
Detects introduction of new delays along one path, and inserts
matching delays on the other paths. The default is inherit.
See also BalanceDelays.
Insert pipeline registers at faster clock rate instead of the
slower data rate. The default is inherit.
See also ClockRatePipelining.
Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. See also ConstrainedOutputPipeline.
Pipeline register distribution, or register retiming. The default
is off. See also DistributedPipelining.
Synthesis attributes for multiplier mapping. The default is none.
See also DSPStyle.
Remove subsystem hierarchy from generated HDL code. The default
is inherit. See also FlattenHierarchy.
Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also InputPipeline.
Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also OutputPipeline.
Number of functionally equivalent resources to map to a single shared resource. The default is 0. See also Resource Sharing.
Number of parallel data paths, or vectors, that are time multiplexed to transform into serial, scalar data paths. The default is 0, which implements fully parallel data paths. See also Streaming.
If this block is not the DUT, the block property settings in the Target Specification tab are ignored.
In the HDL Workflow Advisor, if you use the IP Core Generation
workflow, these target specification block property values are saved
with the model. If you specify these target specification block property
values using hdlset_param, when you open HDL
Workflow Advisor, the fields are populated with the corresponding
values.
Processor/FPGA synchronization mode, specified as a character vector.
You can set this property In the HDL Workflow Advisor, in the Processor/FPGA Synchronization field.
Values: Free running (default) | Coprocessing
- blocking
Example: 'Free running'
Verilog® or VHDL® files for black boxes in your design. Specify the full path to each file, and separate file names with a semicolon (;).
You can set this property in the HDL Workflow Advisor, in the Additional source files field.
Values: '' (default) | character vector
Example: 'C:\myprojfiles\led_blinking_file1.vhd;C:\myprojfiles\led_blinking_file2.vhd;'
IP core name, specified as a character vector.
You can set this property in the HDL Workflow Advisor, in the IP core name field. If this property is set to the default value, the HDL Workflow Advisor constructs the IP core name based on the name of the DUT.
Values: '' (default) | character vector
Example: 'my_model_name'
IP core version number, specified as a character vector.
You can set this property in the HDL Workflow Advisor, in the IP core version field. If this property is set to the default value, the HDL Workflow Advisor sets the IP core version.
Values: '' (default) | character vector
Example: '1.3'
If your DUT is a masked subsystem, you can generate code only if it is at the top level of the model.