Simulink
Simulink® blocks supported for HDL code generation
- Discontinuities
Blocks that define discontinuous states, such as Saturation
and Quantizer
- Discrete
Blocks that define discrete states, such as Discrete-Time
Integrator and Unit Delay
- HDL Operations
Blocks that model HDL components, such as HDL FIFO,
Bit Shift, and Dual Port RAM
- HDL Subsystems
HDL blocks that specify synchronous reset and enable
behavior
- Logic and Bit Operations
Blocks that perform logic and bit operations, such
as Logical Operator and Relational Operator
- Lookup Tables
Blocks that model nonlinearity with lookup tables,
such as 1-D and 2-D Lookup Table
- Math Operations
Blocks that perform mathematical operations, such
as Gain and Sum
- Model Verification
Blocks that perform model verification, such as Assertion
and Check Dynamic Range
- Model-Wide Utilities
Blocks that support model-wide operations, such as
DocBlock and Trigger-Based Linearization
- Ports and Subsystems
Blocks that support ports and subsystems, such as
Inport and Subsystem
- Signal Attributes
Blocks that support signal attributes, such as Data
Type Conversion and Rate Transition
- Signal Routing
Blocks that support signal routing, such as Bus Creator
and Mux
- Sinks
Blocks that receive output from other blocks, such
as Outport and Scope
- Sources
Blocks that provide Input to other blocks, such as
Constant and Sine Wave
- User-Defined Functions
Blocks that support custom functions, such as Fcn
and MATLAB Function